Agilent Technologies 6571A, Руководство по обслуживанию

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80 Principles Of Operation
•
The supply’s output is downprogrammed.
•
The pulse width modulator (described later) is disabled.
•
With the pulse width modulator disabled, the drive signals for the FET regulators are removed, thereby turning off the
power supply output.
•
When OV is reset, the secondary microprocessor generates
OVCLR
(output protection clear), which clears
OVSCR
.
During power initiation, the secondary microprocessor generates an
INHIBIT
signal to hold the supply’s output off for ten
seconds. After 10 seconds
INHIBIT
is removed and the output can be programmed.
CV/CC Control
These circuits are shown in detail on the A5 Control Board schematic, Sheet 3 and include CV (constant-voltage) and CC
(constant-current) control loops. The power supply must act as either a CV or CC supply for any value of load impedance.
Switching between CV and CC mode is done automatically by the CV/CC control circuits at a value of load impedance
equal to the ratio of the programmed voltage value to the programmed current value. A low-level
CV or CC signal is
generated by the applicable Status Comparator (U630) and returned to the secondary interface to indicate that the
corresponding mode (CV or CC) is in effect.
In CV mode, an OR gate diode (D620) conducts and the CV loop regulates the output voltage. A CV Error Amplifier (P/O
U615) compares the programmed voltage signal
CVPROG
(0 to -10V range) to
VMON
, which is the output voltage monitor
output signal of V_DIF Differential Amplifier (P/0 U615). The range of VMON is 0 to +10V, which corresponds to the
zero-to-full scale output voltage of the supply. If the output voltage exceeds the programmed voltage, the OR_GATE signal
goes low, causing the output voltage to decrease to the programmed value. Conversely, if the output voltage is less than the
programmed voltage, OR_GATE goes high to cause the output voltage to increase to the programmed value. An externally
applied dc signal (
VPROG
) can also be used to program the output voltage. A 0 to -5V
VPROG
level produces a proportional
zero-to-full scale output voltage.
In CC mode, an OR gate diode (D615) conducts and the CC loop regulates the output current. A CC Error Amplifier (P/O
U612) compares the programmed current signal
CCPROG (0 to -10V range) to IMON , which is the output current monitor
signal. This signal is produced by measuring the voltage across a current monitor resistor (A6R907) on the A6 Output Filter
Board.
The voltage drop across A6R907 (
±
ISEN) is amplified by 1st I_AMP (U617) and 2nd I_AMP (U612) to produce current
monitoring signal IMON . The range of IMON is 0 to +10V, which corresponds to the zero-to-full scale output current of the
supply. If the output current exceeds the programmed current, the OR_GATE gate signal goes low, causing the output
current to decrease to the programmed value.
Conversely, if the output current is less than the programmed value, the
OR_GATE
signal goes high, causing the output
current to increase to the programmed value. An externally applied differential voltage signal (
±
IP) can also be used to
program the output current. The IP signal is applied to the CC Error Amplifier via the IPROG Amplifier (P/O U618). A 0 to
10V differential input level produces a proportional zero-to-full scale output current.
Switching/Downprogramming Control
These circuits (A5 Control Board schematic, Sheet 3) include a Ramp Generator, Fast-Sense Differential Amplifier,
Summing Amplifier, Divider, Pulse-Width Modulator, Downprogramming Control, and Overvoltage Comparator circuits.
The
OR-GATE
signal (
CV
or
CC
control signal as previously described) is summed with a fixed 40-KHz triangular waveform
produced by the Ramp Generator. An input from the Fast Sense Differential Amplifier also is summed in order to
compensate for sudden transients in the rectified output.
The Ramp Generator derives its output signal from 40KHz pulses received from the Divider circuit. The Divider circuit also
generates output pulses for a Deadtime Latch and an On Latch. The Divider clock input is the 2MHz
ALE_CK
signal from