AEA PAKRATT PK-232, Техническое справочное руководство

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PK-232 TECHNICAL MANUAL CHAPTER 3 – THEORY OF OPERATION
PK232TM Rev. A 5/87 3-3 Page 13
The tones processed by the resonators are rectified in a full-wave diode network
formed by D19 and D20 for the MARK channel, and D22 and D23 for the SPACE chan-
nel. The MARK signal is positive with respect to the voltage reference (VR); the SPACE
signal is negative.
Output signals from both channels are envelope-detected simultaneously by a short and
long time-constant network and summed at the input of U32-B.
After passing through a lowpass filter to remove ripple, the signal is amplified by U32-C,
U34-C and U34-D and then squared. Its logic level is shifted by a TTL inverter U15-C for
use by either an external modem or U6, a Zilog 8536 Counter/Timer and Parallel I/O
Device.
3.2.2 Transmit Function
Digital input signals from the terminal are received by the serial controller and passed to
the microprocessor for action. If ECHO has been commended ON, the input signals are
routed by the serial controller back to the terminal for display.
3.2.2.1 Transmit Circuits
Data to be transmitted is received over the RS-232 serial port and read by Z8530 Serial
Communications Controller U7 under the control of the Z80 microprocessor. The data is
periodically sent over the data bus to the Z8536, U6. The Z8536 translates the data into
a binary string at the correct data rate and routes the binary string to AFSK generator
U40.
The AFSK generator supplies one of two tones to selected RADIO connector J4 or J6,
depending on the position of RADIO 1/Radio 2 switch SW2.
The transmit tone pair produced by the tone generator is selected by FET switch U35.
This switch selects appropriate frequency-determining resistors R164, R165, R157 and
R168, in accordance with the selected operating mode.
In addition, a logic level of five volts DC (5 VDC) or ground is presented at Scope/FSK
receptacle J7, either inverted or normal, for FSK transmitter keying.
At the same time that the generator is keyed, a Push-to-Talk (PTT) signal is supplied to
transistor keyers (Q4 and Q5). The polarity of the keying signal is selected by jumpers
JP2 and JP3 for the two radio receptacles.
This PTT signal is present as long as pulses from the timer in U7 refresh the timeout cir-
cuitry of Q10 and Q3. If for any reason the program fails or becomes disabled, the
timeout circuitry prevents the PTT line from being activated.
3.3 Digital Subsystem
In the following discussion of the Digital Subsystem, the dollar sign ($) indicates hexadeci-
mal numbers.
3.3.1 Z80A Central Processing Unit
The processor, U1, is a Z80A operating at 4.0 MHz. The peripheral chips U6 and U7 cause
system interrupts using the CPU's INT* input (pin 16). The NMI* and BUSRQ* inputs are
unused, as are the RFSH, HALT and BUSAK outputs.