Advantech UNO-2484G, Руководство пользователя

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31 UNO-2484G User Manual
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A.7 Mini PCIe Slot (MINIPCIE)
Supports PCI1.1, PCI1.2 power definition.
Note 1: +3.3V aux is suspend power; power out to 3.3V/1.1A.
Note 2: +3.3V is core power.
Note 3: +1.5V is core power; power out to 1.5V/0.5A.
Pin Signal Description Pin Signal Description
52
+3.3Vaux /
+3.3V
PCI1.1 was +3.3V, PCI1.2 was
+3.3Vaux
51 Reserved NC
50 GND 49 Reserved NC
48 +1.5V 47 Reserved NC
46 NC NC 45 Reserved NC
44 NC NC 43
PIN43_MP -
CIE_PWR -
SEL
The pin to select the Pin 2, 52
power output for +3.3Vaux or
+3.3V (PCI1.1 was Reserved
and PIC1.2 was GND
42 NC NC 41 +3.3Vaux
40 GND 39 +3.3Vaux
38 USB_D+ USB serial data interface com -
pliant to the USB 2.0 specifica -
tion
37 GND
36 USB_D- 35 GND
34 GND 33 PETp0
PCI Express differential trans -
mit pair
32
SMB_ -
DATA
SMBus data signal compliant to
the SMBus 2.0 specification
31 PETn0
30 SMB_CLK 29 GND
28 +1.5V 27 GND
26 GND 25 PERp0
PCI Express differential
receive pair
24 +3.3Vaux 23 PERn0
22 PERST# Functional reset to the card 21 GND
20
W_DIS -
ABLE#
Active low signal. This signal is
used by the system to disable
radio operation on add-in cards
that implement radio frequency
applications. When imple -
mented, this signal requires a
pull-up resistor on the card.
19 Reserved NC
18 GND 17 Reserved NC
Key Key Key Key
16 NC NC 15 GND
14 NC NC 13
12 NC NC 11 REFCLK-
10 NC NC 9 GND
8 NC NC 7 CLKREQ# Reference clock request signal
6 1.5V 5 NC NC
4 GND 3 NC NC
2
+3.3Vaux /
+3.3V
PCI 1.1 is +3.3V, PCI 1.2 is
+3.3V aux
1 WAKE#
Open drain active low signal.
This signal is used to request
that the system return from a
sleep/suspend state to ser -
vice a function-initiated wake
event.