44
2.5 10GB Ethernet
10GBASE-KR support was added to COM Express with revision 3.0 of the specification.
Type 7 supports up to four 10GBASE-KR interfaces. The 10G MAC is located on the Module and the
PHY is located on the Carrier. 10GBASE-KR uses a single transmit and a single receive ac coupled
differential pair for data and a sideband bus for the PHY control and configuration. COM Express
supports both MDIO and I2C control interfaces for the PHY.
The PHY control interfaces are grouped into pairs. 10G Ports 0 and 1 share a common PHY control
interface and 10G ports 2 and 3 share a common PHY control interface. The PHY interface selection is
made using the 10G_PHY_CAP_01 and 10G_PHY_CAP_23 pins. The Carrier design can select the
PHY that is appropriate for the design. The Module designer
should
design the module in such a way
that it can provide the PHY interface that is selected regardless of the capabilities of the silicon used on
the Module. Appropriate level shifters
shall
be used.
A two wire I2C bus (designated 10G_LED_SDA and 10G_LED_SCL) is defined to serialize the
outbound (Module to Carrier) MAC LED and PHY strapping signals, conserving COM Express pins. The
Carrier
should
use a PCA9539 or compatible I2C I/O expander. The Carrier PCA9539
shall
be mapped
to I2C address 1110 100x (x=R/W bit). Table 14 below defines the port pin mapping for the I/O
expander.
There are two pairs of PHY strapping signals defined. The first pair is designated as 10G_PHY_CAP_01
and 10G_PHY_CAP_23. These are actual COM Express pins. They are inputs to the COM Express
Module. The Carrier
may
either tie these lines to GND or leave them NC on the Carrier. If
10G_PHY_CAP_01 is tied low on the Carrier, this indicates to the Module that the PHY on the Carrier for
10G interfaces 0 and 1 can be configured by either I2C or by MDIO. If the Carrier leaves the line NC,
then this indicates to the Module that the Carrier PHY can only be configured by MDIO. Similarly for
strap signal 10G_PHY_CAP_23 and 10G interfaces 2 and 3.
The second pair of PHY strapping signals are outputs from the Module, serialized onto the
10G_LED_Sxx I2C bus. They are desterilized on the Carrier I/O expander and
may
used to set Carrier
PHY strapping pins to set the desired Carrier PHY configuration mode, if the PHY is capable of multiple
configuration modes.
This arrangement with a pair of input straps (telling the Module what configuration modes are possible
on the Carrier PHY) and a pair of serialized output straps (telling the Carrier PHY what configuration
mode to use) allow Module designs that can use a variety of PHYs. In particular, Intel Broadwell DE
Modules that can be used with either Intel "Coppervale" PHYs or with Inphy / Cortina PHYs can be
realized. Block diagram examples may be found in 2.5.2
‘Example 10 GB Ethernet Designs’ of this
document.
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Страница 56: ...2 5 2 2 2016 Silicon 10GbE Copper Implementation Figure 9 10G Ethernet Design for Copper PHY with Broadwell DE...
Страница 57: ...2 5 2 3 Future Silicon 10GbE Fiber Implementation Figure 10 10G Ethernet Design for Fiber PHY with Future SoC...
Страница 58: ...2 5 2 4 Future Silicon 10GbE Copper Implementation Figure 11 10G Ethernet Design for Copper PHY with Future SoC...