Appendix A Programming the Watchdog Timer ........ 19
A.1
Programming the watchdog timer ............................... 2 0
Appendix B System Assignments .............................. 23
B.1
System I/O ports ............................................................ 2 4
B.2
DMA channel assignments ........................................... 2 5
B.3
Interrupt assignments ................................................... 2 6
B.4
1st MB memory map ..................................................... 2 7
Appendix C LVDS Connection ................................... 29
C.1
LVDS Introduction ......................................................... 3 0
C.2
LVDS Pin assingments .................................................. 3 1
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