Advantech ROM-3420CD-MDA1E, Руководство пользователя

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35 ROM-3420 User Manual
Chapter 3
S
oftware
Functionality
3. The transfer rate supported
When a single port is active, the pixel clock rate is up to 264 MHz
When both LVDS ports are active, you have to follow below condition:
1. Each pixel clock rate may be up to 220 MHz**
2. The sum of pixel clock rates is up to 240 MHz
3.8.6 Network Setup
If you would like to use DHCP mode instead, please goes to /etc/rc.d/rc.conf, and set
IPADDR0 to “dhcp”.
If you prefer to use static IP as default, you should goes to /etc/rc.d/rc.conf, and set
IPADDR0 to the IP to be used. And the NETMASK0 should be changed to corre-
sponding netmask as well.
3.8.7 Storage (SATA /eMMC/SD Card)
The storages devices are named as follows:
3.8.8 3G Sample Code
The code of 3glink, we have tried this command in 3 G test (Section 1.8).
#!/bin/bash
echo
"Send AT commands..."
pppd connect 'chat
‐
v
‐
s
‐
t 10 "" "AT" "" "ATDT*99#" "CONNECT" ""'
user username password password /dev/ttyUSB2 460800 nodetach crtscts
debug usepeerdns defaultroute &
Note! In Single Display mode, the pixel clock of HDMI is up to 264 MHz, each
other is up to 200 MHz.
In Dual Display mode, the pixel clock of HDMI is up to 240 MHz, each
other is up to 200 MHz.
Device Name
SATA /dev/sda
eMMC /dev/mmcblk0
SD card /dev/mmcblk1