Advantech PCM-4380F-M0A2E, Руководство пользователя

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PCM-4380 User Manual 92
Appendix C DC Input Timing
(Reference as ATX 2.2)
C.1 DC Input Timing
The power-on time is defined as the time from when PS_ON# is pulled
low to when the +12 VDC, +5 VDC, and +3.3 VDC outputs are within
the regulation ranges. The power-on time shall be less than 500 ms
(T1 < 500 ms).
The output voltages shall rise from ≤ 10% of nominal to within the regu-
lation ranges within 0.1 ms to 20 ms (0.1 ms ≤ T2 ≤ 20 ms). There must
be a smooth and continuous ramp of each DC output voltage from 10% to
90% of its final set-point within the regulation band. The smooth turn-on
requires that, during the 10% to 90% portion of the rise time, the slope of
the turn-on waveform must be positive and have a value of between 0 V/
ms and [ Vout, nominal / 0.1] V/ms. Also, for any 5 ms segment of the
10% to 90% rise time waveform, a straight line drawn between the end
points of the waveform segment must have a slope
≥ [ Vout, nominal / 20]
V/ms.
Table C.1: DC Input Timing Table
Signal Type Timing Control
Power-on Time T1 < 500 ms
Power-on rise time
0.1 ms
≤
T2
≤
20 ms