Advantech PCI-1713, Руководство пользователя

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Chapter 4 Register Structure and Format 23
4.3 A/D Data — BASE+0 and BASE+1
These two bytes, BASE+0 and BASE+1, hold the result of A/D
conversion data. The 12 bits of data from the A/D conversion are
stored in BASE+1 bit 3 to bit 0 and BASE+0 bit 7 to bit 0.
Table 4-2: Register for channel number and A/D data
AD11 ~ AD0 Result of A/D Conversion
AD0 is the least significant bit (LSB) of the A/D data, and AD11 is the
most significant bit (MSB).
4.4 Software A/D Trigger — BASE+0
You can trigger an A/D conversion by software, the card’s on-board
pacer or an external pulse. Bit 2 to bit 0 of register BASE+6 can
select the trigger source (see page 27 and page 28 for the register
layout of BASE+6 and programming information). If you select
software triggering, a write to the register BASE+0 with any value
will trigger an A/D conversion.
4.5 A/D Channel Range Setting —
BASE+2
Each A/D channel has its own input range, controlled by a range code
stored in the on-board RAM. If you want to change the range code
for a given channel, select the channel as the start channel and the
stop channel in the registers of BASE+4 and BASE+5 (described in
the next section), and then write the range code to BASE+2 bit 0 to
bit 2 and bit 4.
Read A/D Data
Bit # 7 6 5 4 3 2 1 0
BASE+1 AD11 AD10 AD9 AD8
BASE+0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0