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MIC-3332 User Manual 44
C.1 Overview
For the MIC-3332 project, a CPLD (10M02SCU169I7G) from the Altera Max 10 fam -
ily is used.
C.1.1 CPLD Functional Blocks
Figure C.1 CPLD Block Diagram
C.2 Features
The following functional blocks are realized inside the CPLD:

LPC interface
– Connects the LPC bus to the CPLD internal logic, Port80 diagnostic interface
– realized as an LPC target
• supports IO access

Clock Generator
– Derivate internal needed clocks and timing pulses from 50MHz CPLD base
clock

Watchdog
– Watchdog function can cause system reset
– It can be called by writing value to registers from the LPC interface

Port 80 Diag
– POST LED control

LED
– Indicates the current state of the system

Register interface
– contains all control and state signals

Synchronizer and Debouncer
– Synchronizes all external signals into CPLD clock domain
– Debounces all input from switches and jumpers with mechanical contacts