Advantech ASR-3100PP-R11A1E, Руководство пользователя

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ASR-3100 Series User Manual 42
 Enable SMX
Enables Safer Mode Extensions.
 Execute Disable Bit
This item specifies the Execute Disable Bit Feature. The settings are Enabled
and Disabled. The Optimal and Fail-Safe default setting is Enabled. If Disabled
is selected, the BIOS forces the XD feature flag to always return to 0.

Hardware Prefetcher
Hardware Prefetcher is a technique that fetches instructions and/or data from
memory into the CPU cache memory well before the CPU needs it, so that it can
improve the load-to-use latency. Set to enable or disable.
 Adjacent Cache Line Prefetch
The Adjacent Cache-Line Prefetch mechanism, like automatic hardware
prefetch, operates without programmer intervention. When enabled through the
BIOS, two 64- byte cache lines are fetched into a 128-byte sector, regardless of
whether the additional cache line has been requested or not. Set to enable or
disable.
 DCU Streamer Prefetch
Enable prefetch of next L1 data line based upon multiple loads in same cache
line.
 DCU IP Prefetcher
Enable prefetch of next L1 line based upon sequential load history.
 DCU Mode
MSR 31h Bit[0] - A write of 1 selects the DCU mode as 16KB 4-way with ECC.
 AES-NI
Enable/disable AES-NI support.
3.2.3.2 Advanced Power Management Configuration
Power technology default is “Energy Efficient”.