B-1
Section 61246001L2-5, Issue 2
61246001L2-5B
Appendix B
DS0 Blocking
ADTRAN has implemented the DS0 blocking feature
enabling the HDSL system to remain transparent to
customer data. This allows ADTRAN products to
comply with the transparency requirements of
Bellcore TA-NWT-001210. However, when the
circuit is provisioned for ESF operation, this
transparency results in a condition described below.
If a customer of a Fractional T1 service fills any of the
unused DS0 channels with information other than an
all 1s idle code, the ADTRAN HDSL system will
block this information from reaching the remote end
of the circuit. This forces information in those DS0
channels to be an all 1s idle code.
The result of this blocking is that the CRC checksum
delivered to the remote end will not match the
checksum calculated by the remote T1 CSU. This
implies errors are being made on the loop when
actually the blocking function created the CRC errors.
Enabled DS0 channels pass error-free.
In order to avoid this condition, Fractional T1
customers are encouraged to fill the unused timeslots
with an idle code. This is a common capability on
Fractional T1 CSU/DSU, D4 channel banks, and other
CPE devices capable of connecting to Fractional T1
service.
