ADLINK Technology NuDAQ PCI-9114DG, Руководство пользователя, Страница: 40 / 95

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Operation Theorem
Signal Range
The proper signal range is important for data acquisition. The input signal
may be saturated if the A/D gain is too large. Sometimes, the resolution may
be not enough if the signal is small. The maximum A/D signal range of
PCI-9114 is +/- 10 volts when the programmable gain value is 1. The A/D gain
control register controls the maximum signal input range. The signal gain is
programmable with 4 levels (1,10,100,1000) or (1,2,4,8). The signal range of
the 32 channels will be identical all the time even if the channel number is
scanning. The available signal polarity on PCI-9114 is bi-polar only, however,
the 16-bit high resolution of PCI-9114 can cover all the 12-bits uni-polar
applications.
4.1.3 A/D Trigger Source Control
The A/D conversion is started by a trigger source, and then the A/D
converter will start to convert the signal to a digital value. In PCI-9114,
two internal sources can be selected: the software trigger or the timer
pacer trigger. The A/D operation mode is controlled by A/D trigger mode
register. Total two trigger sources are provided in the PCI-9114. The
different trigger conditions are specified as follows:
Software trigger (TSSEL=0)
The trigger source is software controllable in this mode. That is, the A/D
conversion is starting when any value is written into the software trigger
register. This trigger mode is suitable for low speed A/D conversion.
Under this mode, the timing of the A/D conversion is fully controlled by
software. However, it is difficult to control the fixed A/D conversion rate
unless another timer interrupt service routine is used to generate a fixed
rate trigger. Refer to interrupt control section (section 4.2) for fixed rate
timer interrupt operation.
Timer Pacer Trigger (TSSEL=1)
An on-board timer / counter chip 8254 is used to provide a trigger source for
A/D conversion at a fixed rate. Two counters of the 8254 chip are cascaded
together to generate trigger pulse with precise period. Please refer to section
4.3 for 8254 architecture. This mode is ideal for high speed A/D conversion. It
can be combined with the FIFO half-full interrupt or EOC interrupt to transfer
data. It is also possible to use software FIFO polling to transfer data. The A/D
trigger, A/D data transfer and Interrupt can be set independently, most of the
complex applications can thus be covered. It's recommended using this
mode if your applications need a fixed and precise A/D sampling rate.