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nanoX-BT
7.3.7.
PCI and PCIe
Feature
Options
Description
PCI and PCIe
Info only
PCI Common Settings
Info only
PCI Latency
32 PCI Bus Clocks
64 PCI Bus Clocks
96 PCI Bus Clocks
128 PCI Bus Clocks
160 PCI Bus Clocks
192 PCI Bus Clocks
224 PCI Bus Clocks
248 PCI Bus Clocks
Value to be programmed into PCI latency timer register.
VGA Palette Snoop
Disabled
Enabled
Enables or Disables VGA palette registers snooping.
PERR# Generation
Enabled
Disabled
Enable or Disable the PCI Express port 1 in the chipset.
SERR# Generation
Enabled
Disabled
Enables or Disables PCI Device to generate SERR#.
PCI Express Settings
Info only
Relaxed Ordering
Disabled
Enabled
Enables or Disables PCI Express device relaxed ordering.
Extended Tag
Disabled
Enabled
If Enabled, allows device to use 8-bit tag field as a requester.
No Snoop
Disabled
Enabled
Enables or Disables PCI Express device No Snoop option.
Maximum Payload
Auto
128 Bytes
256 Bytes
512 Bytes
1024 Bytes
2048 Bytes
4096 Bytes
Set maximum payload of PCI Express device or allow system BIOS
to select the value.
Maximum Read Request
Auto
128 Bytes
256 Bytes
512 Bytes
1024 Bytes
2048 Bytes
4096 Bytes
Set maximum read request size of PCI Express device or allow
system BIOS to select the value.
PCI Express Link Register Settings
Info only
ASPM Support
WARNING: Enabling ASPM may cause some
PCI-E devices to fail
Disabled
Auto
Force L0s
Set the ASPM Level: Force L0s - Force all links to L0s
Auto - BIOS auto configure
Disabled - Disables ASPM
Extended Synch
Disabled
Enabled
If enabled, allows generation of Extended Synchronization patterns.
Link Training Retry
Disable
2
3
5
Defines number of retry attempts software will take to retrain the
link if previous training attempt was unsuccessful.
Link Training Timeout (Us)
1000
Defines number of microseconds software will wait before polling
'Link Training' bit in Link Status register. Value range from 10 to
10000 uS.