ADLINK Technology COM Express Express-BL, Руководство пользователя

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Page 26
3.3.16. General Purpose I/O (GPIO)
Signal Pin # Description I/O PU/PD Comment
GPO[0] A93 General purpose output pins. O 3.3V PU 10K 3.3V After hardware RESET
output low
GPO[1] B54 General purpose output pins. O 3.3V PU 10K 3.3V After hardware RESET
output low
GPO[2] B57 General purpose output pins. O 3.3V PU 10K 3.3V After hardware RESET
output low
GPO[3] B63 General purpose output pins. O 3.3V PU 10K 3.3V After hardware RESET
output low
GPI[0] A54 General purpose input pins.
Pulled high internally on the module. I 3.3V PU 10K 3.3V
GPI[1] A63 General purpose input pins.
Pulled high internally on the module. I 3.3V PU 10K 3.3V
GPI[2] A67 General purpose input pins.
Pulled high internally on the module. I 3.3V PU 10K 3.3V
GPI[3] A85 General purpose input pins.
Pulled high internally on the module. I 3.3V PU 10K 3.3V
3.3.17. Serial Interface Signals
Signal Pin # Description I/O PU/PD Comment
SER0_TX A98 General purpose serial port transmitter (TTL level output) O CMOS Power rail tolerance 5V, 12V
There shall be PD on carrier
board
SER0_RX A99 General purpose serial port receiver (TTL level input) I CMOS Power rail tolerance 5V, 12V
SER1_TX A101 General purpose serial port transmitter (TTL level output) O CMOS Power rail tolerance 5V, 12V
There shall be PD on carrier
board
SER1_RX A102 General purpose serial port receiver (TTL level input) I CMOS Power rail tolerance 5V, 12V
3.3.18. Power and System Management
Signal Pin # Description I/O PU/PD Comment
PWRBTN# B12 Power button to bring system out of S5 (soft off), active on falling edge. I 3.3VSB PU 10k
3.3VSB
SYS_RESET# B49 Reset button input. Active low request for module to reset and reboot. May
be falling edge sensitive. For situations when SYS_RESET# is not able to
reestablish control of the system, PWR_OK or a power cycle may be used. I 3.3V PU 10k 3.3V
CB_RESET# B50 Reset output from module to Carrier Board. Active low. Issued by module
chipset and may result from a low SYS_RESET# input, a low PWR_OK
input, a VCC_12V power input that falls below the minimum specification, a
watchdog timeout, or may be initiated by the module software. O 3.3V PU 1K 3.3V
PWR_OK B24 Power OK from main power supply. A high value indicates that the power is
good. This signal can be used to hold off Module startup to allow carrier
based FPGAs or other configurable devices time to be programmed. I 3.3V PU 100k
3.3VSB Should have
weak pull up