ADLINK Technology AmITX-BT-I, Руководство пользователя

Страница: 31 / 68

AmITX-BT-I Page 31
4.2.13. SPI Header
2x6-pin 2.0 pitch standard wafer connector
Type Signal Pin # Pin # Signal Type
CLK 1 2 SB3V3 PWR
I CS0# 3 4 ADDIN IO
I CS1# 5 6 NC -
I MOSI 7 8 ISOLATE IO
O MISO 9 10 GND PWR
IO SPI_IO2_#WP 11 12 SPI_IO3_#HOLD IO
Signal Description
CLK Serial Clock
SB3V3 3.3V Standby Voltage power line. Normally output power, but when Motherboard is turned off then the on-board
SPI Flash can be 3.3V power sourced via this pin.
CS0# CS0# Chip Select 0, active low.
ADDIN ADDIN input signal must be NC.
MOSI Master Output, Slave Input
ISOLATE# The ISOLATE# input, active low, is normally NC, but must be connected to GND when loading SPI flash. Power
Supply to the Motherboard must be turned off when loading SPI flash. The pull up resistor is connected via diode
to 5VSB.
MISO Master Input, Slave Output
SPI_IO2_#WP SPI Data I/O: A bidirectional signal used to support the new Dual
IO Fast Read, Quad IO Fast Read and Quad Output Fast Read modes. This signal is not used in Dual Output
Fast Read mode.
SPI_IO3_#HOLD SPI Data I/O: A bidirectional signal used to support the new Dual
IO Fast Read, Quad IO Fast Read and Quad Output Fast Read modes. This signal is not used in Dual Output
Fast Read mode.
1 2