Actel ProASIC3/E, Руководство пользователя, Страница: 57 / 106

Step 6 – Perform Timing Simulation with Back-Annotated Timing
ProASIC3/E Starter Kit User’s Guide and Tutorial 57
14. From Designer, click Back-Annotate in the Design Flow window. This opens the Back-Annotate dialog box, shown
in Figure 7-36 .
Figure 7-36. Back-Annotate Dialog Box
15. Accept the default settings and click OK . The Back-Annotate icon turns green.
16. Save and close Designer. From the File menu, click Exit . Click Yes to save the design before closing Designer.
Designer saves all the design information in an *.adb file.
The file Top.adb appears under the Designer Files of the File Manager. To reopen the file, right-click the file and
select
Open in Designer.
Step 6 – Perform Timing Simulation with Back-Annotated Timing
After completing the place-and-route and back annotation of the design, perform a timing simulation with the
ModelSim HDL simulator.
To perform a timing simulation:
1. Click the Simulation icon in the Libero IDE Design Flow window, or right-click the Top.vhd file in the Design
Hierarchy tab and select Run Post-Layout Simulation .
2. This launches the ModelSim Simulator that compiles the back annotated VHDL netlist file and testbench. Once
the compilation completes, the simulator runs for 1000 ns and a Wave window opens to display the simulation
results. From the ModelSim menu, select
Simulate > Run > Run All to execute the full simulation time defined in
the testbench.
3. Scroll in the Wave window to verify that the counter works correctly. Use the zoom buttons to zoom in and out as
necessary.