Acromag IP440 Series, Руководство пользователя

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SERIES IP440 INDUSTRIAL I/O PACK 32-CHANNEL ISOLATED DIGITAL INPUT MODULE
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Note that the inputs of this device are bipolar, and may be
connected in any direction with respect to the port common.
Further, do not confuse port commons with signal ground. For
the IP440, port common only infers that this lead is connected
common to the 8 inputs of the port (a separate port common for
each port). Likewise, the port commons of the IP440 input
module and IP445 output module are normally not connected
together for loopback interconnection (see Drawing 4501-603).
Noise and Grounding Considerations
Input lines of the IP440 are optically isolated between the
logic and field input connections. Likewise, separate port
commons facilitate port-to-port isolation. Consequently, the field
I/O connections are isolated from the carrier board and
backplane, thus minimizing the negative effects of ground
bounce, impedance drops, and switching transients. However,
care should be taken in designing installations to avoid
inadvertent isolation bridges, noise pickup, isolation voltage
clearance violations, equipment failure, or ground loops.
IP Logic Interface Connector (P1)
Table 2.2: Standard Logic Interface Connections (P1)
Pin Description Number Pin Description Number
GND 1 GND 26
CLK 2 +5V 27
Reset* 3 R/W* 28
D00 4 IDSEL* 29
D01 5 DMAReq0* 30
D02 6 MEMSEL* 31
D03 7 DMAReq1* 32
D04 8 IntSel* 33
D05 9 DMAck0* 34
D06 10 IOSEL* 35
D07 11 RESERVED 36
D08 12 A1 37
D09 13 DMAEnd* 38
D10 14 A2 39
D11 15 ERROR* 40
D12 16 A3 41
D13 17 INTReq0* 42
D14 18 A4 43
D15 19 INTReq1* 44
BS0* 20 A5 45
BS1* 21 STROBE* 46
-12V 22 A6 47
+12V 23 ACK* 48
+5V 24 RESERVED 49
GND 25 GND 50
An Asterisk (*) is used to indicate an active-low signal.
BOLD ITALIC Logic Lines are NOT USED by this IP Model.
P1 of the IP module provides the logic interface to the mating
connector on the carrier board. The pin assignments of P1 are
standard for all IP modules according to the Industrial I/O Pack
Specification (see Table 2.2). This connector is a 50-pin female
receptacle header (AMP 173279-3 or equivalent) which mates to
the male connector of the carrier board (AMP 173280-3 or
equivalent). This provides excellent connection integrity and
utilizes gold-plating in the mating area.
Threaded metric M2 screws and spacers are supplied with the IP
module to provide additional stability for harsh environments (see
Drawing 4501-434 for assembly details). Field and logic side
connectors are keyed to avoid incorrect assembly.
3.0 PROGRAMMING INFORMATION
ADDRESS MAPS
This board is addressable in the Industrial Pack I/O space to
control the configuration and status monitoring of 32 digital input
or event channels.
This board operates in two modes: Standard Mode and
Enhanced Mode. Standard Mode provides digital input voltage
monitoring of 32 isolated signal lines. In Standard Mode, each
input line is configured as a simple input without interrupts. Data
is read from (or written to) one of eight groups (ports) as
designated by the address and read and write signals. The ASIC
of this model is capable of I/O, but this model is intended for input
only. A Mask Register is used to disable writes to I/O ports
designed for input only. Enhanced Mode includes the same
functionality of Standard Mode, but adds access to 32 additional
event sense inputs connected to each input point of ports 0-3.
Individual inputs also include selectable hardware debounce in
Enhanced Mode. For event sensing, the Enhanced Mode allows
a specific input level transition (High-to-Low, Low-to-High, or
Change-of-State) to be detected and optionally generate an
interrupt.
Memory is organized and addressed in separate banks of
eight registers or ports (eight ports to a bank). The Standard
Mode of operation addresses the first group of 8 registers or ports
(ports 0-3 for reading inputs, Ports 4, 5, & 6 which are not used
on this model, and Port 7 which is the Mask Register). The mask
register is included to mask writes to input points, since the input
points of this model are intended for input only, while the digital
ASIC is capable of output control. If the Enhanced Mode is
selected, then 3 additional banks of 8 registers are accessed to
cover the additional functionality in this mode (events, interrupts,
and debounce). The first bank of the Enhanced Mode (bank 0) is
similar in operation to the Standard Mode. The second bank
(bank 1) provides event sense and interrupt control. The third
bank is used to configure the debounce circuitry to be applied to
input channels in the Enhanced Mode. Two additional mode-
independent registers are provided to enable the interrupt request
line, generate a software reset, and store the interrupt vector.
The I/O space may be as large as 64, 16-bit words (128
bytes) using address lines A1..A6, but the IP440 uses only a
portion of this space. The I/O space address map for the IP440
is shown in Table 3.1. Note the base address for the IP module
I/O space (see your carrier board instructions) must be added to
the addresses shown to properly access the I/O space. All
accesses are performed on an 8-bit byte basis (D0..D7).
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