AP513 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 34 -
http://www.acromag.com
- 34 -
www.acromag.com
3.4.5.1 Interrupt Generation
•
LSR is by any of the LSR bits [4:1]. See IER bit [2] description on the
previous page.
•
RXRDY is by RX trigger level.
•
RXRDY Time-out is by a 4-char plus 12 bits delay timer.
•
TXRDY is by TX trigger level or TX FIFO empty
•
MSR is by any of the MSR bits [3:0].
•
Receive Xoff/Xon/Special character is by detection of a Xoff, Xon or
Special character.
•
CTS# is when its transmitter toggles the input pin (from LOW to
HIGH) during auto CTS flow control enabled by EFR bit [7] and
selection on MCR bit [2].
•
RTS# is when its receiver toggles the output pin (from LOW to
HIGH) during auto RTS flow control enabled by EFR bit [6] and
selection on MCR bit [2].
•
Wake-up indicator is when the UART wakes up from the sleep
mode.
3.4.5.2 Interrupt Clearing
•
LSR interrupt is cleared by a read to the LSR register.
•
RXRDY interrupt is cleared by reading data until FIFO falls below the
trigger level.
•
RXRDY Time-out interrupt is cleared by reading RHR.
•
TXRDY interrupt is cleared by a read to the ISR register or writing to
THR.
•
MSR interrupt is cleared by a read to the MSR register.
•
Xoff/Xon interrupt is cleared by reading ISR.
•
Special character interrupt is cleared by a read to ISR.
•
RTS# and CTS# status change interrupts are cleared by a read to the
MSR register.
•
Wake-up indicator is cleared by a read to the INT0 register.
Table 3.12 Interrupt Source and
Priority Level
PRIORITY
LEVEL
ISR BITS
Bit5 to Bit0
Source of the Interrupt
1
000110
Receiver Line Status (see LSR bits 1-4)
2
000100
Received Data Ready or Trigger Level
reached.
2
001100
Receive Data Time Out.
3
000010
Transmitter Holding Register Empty
4
000000
MSR (Modem Status Register)
5
010000
Received Xoff signal special character
