AcroPack Series ACPS3320
CompactPCI-Serial Carrier Board
- 15 -
Refer to the PICMG CPCI-S specification for additional information on the
CPCI-S signals.
Table 3 CPCI-S P1 CONNECTIONS
Pin
A
B
C
01
+12V
STANDBY
GND
02
GND
I
2
C_SCL
I
2
C_SDA
03
1_
1_USB3_Tx-
GA0
04
GND
1_USB2-
05
1_
1_PE_Tx00-
GND
06
GND
1_
1_PE_Tx02-
D
E
F
01
+12V
+12V
GND
02
GND
reserved
reserved
03
1_
1_USB3_Rx-
GA1
04
GND
P
PE_CLKIN-
05
1_
1_PE_Rx00-
GND
06
GND
1_
1_PE_Rx02-
G
H
I
01
+12V
+12V
GND
02
GND
RST#
WAKE_OUT#
03
SATA_SDI
SATA_SDO
GA2
04
GND
1_
1_SATA_Tx-
05
1_
1_PE_Tx01-
GND
06
GND
1_
1_PE_Tx03-
J
K
L
01
+12V
+12V
GND
02
GND
PCIE_EN#
SYSEN#
03
SATA_SCL
SATA_SL
GA3
04
GND
1_
1_SATA_Rx-
05
1_
1_PE_Rx01-
GND
06
GND
1_
1_PE_Rx03-
Notes (Table 3):
1.
Hash (#) is used to indicate an active-low signal.
2.
BOLD ITALIC Logic Lines are NOT USED by the carrier board.
The ACPS3320 field I/O connections are made through the CPCI-S rear
backplane connectors P2 and P3. Tables 5 and 6 indicate the pin assignments
for P2 and P3.