Acer
Acer –LCD-X163W
8
4.2.2
DDC signals
DDC signals: 5V@50mA TTL level
4.3 Timing requirements
Scan Frequency
Condition
Specification
Horizontal
Sync polarity: (+) or (-)
31 ~ 57 KHz.
Vertical
Sync polarity: (+) or (-)
56-70Hz
Out of range
Excluding
Horizontal 31~57 KHz or
Vertical 56-70 Hz
panel DCLK<= 85 MHz
Message “Input Not Supported” on screen
4.4DDC data
4.4.1
EDID Standard Compliance
EDID File Format : VESA’s EDID Standard Version #3, Revision #0,
EDID Structure : Version #1, Revision #3.
EDID Data Table : See the attached table (for example)
X163W EDID table
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
00 FF FF FF FF FF FF 00 04 72 58 00 5C AA 80 80
1
08 12 01 03 08 23 14 78 E8 55 45 A3 55 4A 97 27
2
15 50 54 33 0C 00 61 46 01 01 01 01 01 01 01 01
3
01 01 01 01 01 01 8A 21 56 B0 51 00 1B 30 48 90
4
13 00 58 C1 10 00 00 1C 00 00 00 FD 00 38 46 1F
5
39 09 00 0A 20 20 20 20 20 20 00 00 00 FF 00 31
6
32 33 34 35 36 37 38 39 30 41 42 0A 00 00 00 FC
7
00 58 31 36 33 57 0A 20 20 20 20 20 20 20 00 43
X163W EDID table detail description:
Address
Vendor Product Identification
Description
00~07h ID information Header
ID information Header
08~09h
ID Manufacturer
Name
ACR
0A~0Bh ID Product Code
0058
0C~0Fh ID Serial Number
8080AA5C
10h
Week of Manufacture
08
11h
Year of Manufacture
2008
12h
Version Number
1
13h
Revision Number
3
14h
Analog/Digital Signal Level [7] Analog Signal Level
Signal Level Standard [6:5] 0.700, 0.300 (1.000Vp-p)
Setup [4] No Blank -to-black Setup
Содержание X163W
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Страница 43: ...Acer Acer LCD X163W 42 06 Schematics and Layouts 6 1 PI BD Layout ...
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