Acer Veriton 7600GTR, Руководство по обслуживанию

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35 Chapter 2
Advanced Chipset Features
The following screen shows the Advanced Chipset Features.
The following table describes each Advanced Chipset Features parameter. Settings in boldface are the default
and suggested settings.
Parameter Description Options
DRAM Timing Selectable Selects whether DRAM timing is controlled by the
SPD (Serial Presence Detect) EEPROM on the
DRAM module. Setting to By SPD enables DRAM
timings to be determined by BIOS based on the
configurations on the SPD. Selecting Manual allows
users to configure the DRAM timings manually. By SPD
Manual
CAS Latency Time This controls the timing delay (in clock cycles)
before SDRAM starts a read command after
receiving it. Settings: 2, 2.5, 3 (clocks). 2 (clocks)
increases the system performance the most while 3
(clocks) provides the most stable performance. 2T , 2.5T, 3T
Active to Precharge Delay The field specifies the idle cycles before
precharging an idle bank. 5T, 6T, 7T, 8T
DRAM RAS# to CAS# Delay This field allows you to set the number of cycles for
a timing delay between the CAS and RAS strobe
signals, used when DRAM is written to, read from
or refreshed. Fast speed offers faster performance
while slow speed offers more stable performance. 2T, 3T, 4T