Acer Picasso, Руководство по обслуживанию

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1-14 Hardware Specifications and Configurations
System Block Diagram
0
Figure 1-7. System Block Diagram
SIM
c
a
rd
US
B2
3G
c
a
rd
WIFI
BT_MIC
BT
WM-
8
9
0
3
G
E
N1_I2C(1.8V)
L
ight
Se
ns
or
T
o
u
ch
S
cr
een
I2
C
L
evel s
h
ifter
G
E
N1_I2C(3.3V
)
Audi
o Code
c
GYRO PM
U-
3
0
5
0
Acceler
o
m
eter
KX
T
F
9-4100
A
L
3000A
SD
IO
Car
d
Sl
ot
US
B3
ULPI
SD
IO
1(1.8V
)
SD
IO
1
to
U
S
B boar
d
HDM
I
HDM
I C
onn.
eM
M
C
NAND
4.3 /
4.41
8
b
its HS
MMC
LV
DS br
idge
RGB (1.8
V)
HDM
I
5M
CAM
E
RA
M
odul
e
CSI A (1.2V)
DDR
NA
ND
Ct
rl
LPDDR2
X 1
512M
B
/
1G
B
V
I&D
SI/
C
SI
OS
C
,P
LL,
LC
D
VGA
AUDI
O
US
B
+
mi
n
i-B
connect
o
r
SD
IO
3
HS
IC
co
re
&
fu
se
D
D
R
2 32bi
ts
Nvidia Tegra T20
12M
H
z
D
D
C
_I2C(5V)
ULPI
to
US
B
(SM
S
C U
S
B
3315)
UL
PI (1
.8V)
2M
CAM
E
RA M
odul
e
10.1"
LV
DS pane
l
CSI B (1.2V)
UART
3
(1
.8
V)
SD
IO
3(3.3V
)
B
C
4329
WI
F
I / B
T
m
odul
e
G
P
S M
o
dul
e
UART2
(
1
.8
V)
UART
DAP4
(1
.8
V)
to
U
S
B boar
d
A
u
di
o Code
c
W
o
lf
so
n W
M
8903
H
eadP
hone
US
B1
DAP1
(1
.8
V)
F
ront
M
IC
SPKR
A
M
P
AL
C
1
0
5
IN
T
S
p
ea
ker
Re
a
r M
IC
FM
2018
Ech
o
& N
o
is
e C
a
n
cel
Fl
as
h L
E
D
Cont
ro
ll
er
2M
CAM
E
R
A
Mo
d
u
le
5
M
C
A
M
ERA
M
o
dul
e
CA
M
_
I2C(1.
8V
)
Fl
as
h L
E
D
CA
ND
O
+
A
tm
el
+5V_
AL
W
Inp
u
t
PW
R_I2C
(1.8V)
Te
mp
er
a
tu
re
Se
ns
or
NCT
-1008
Com
pas
s
A
K
M
8975C
+1
V_
S
M
0
fo
r C
P
U
+
1
.2V
_SM
1 f
o
r CP
U
+
3
.7V
_SM
2
L
D
O
0 ~ 9 f
o
r CP
U
P
M
U
T
I T
P
S658621C
GPIO
P-S
E
N
S
OR
CM
3607
I2C
F
M
2018
EC_
S
M
B
2S1P
B
A
T
T
SP
I
SP
I R
O
M
E
C
K
B
930
E
C_RE
S
MUE
G
E
N2_I2C(1.8V)
I2
C
L
evel s
h
ifter
ON/OFF#
A
P
_SM
B
(3.3V
)
A
P
_
SM
B
(3.3V
)
EDID
T2
0
GE
N
2
I
2
C
GPI
O
EC_
S
M
B
DAP4
(1.2V,1.8V)
A
P
_
SM
B
(3.3V
)
SG_PICASSO.book Page 14 Thursday, March 10, 2011 8:08 AM