Circuit Operation Theory
API Confidential
No Copy/Reproduction Allowed
2-5
2.1.4. 99sl Autosync Deflection Controller circuit
+
1
2
3
VI
VO
GND
N.C.
FOCUS
HUNLOCK
SCL
SDA
ASCOR
VCC
DGND
SGND
HDRY
PGND
HPLL2
I.C.
BDRV
HFLB
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CLBL
HSYNC
VSYNC
VOUT1
VOUT2
EWDRV
VAGC
VCAP
VREF
HPLL1
HBUF
HREF
HCAP
BIN
BSENS
BOP
XRAY
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
+
D319
C395
C396
R331
C397
L306
R392
R393
R3922
C391
R397
ZD311
Q391
R3912
R3914
R3913
R3911
R395
R320
R394
C392
C350
IC303
C355
C352
C356
C353
C358
R396
R339
VR301
R351
C359
IC304
C348
R3924
R3921
R3925
C354
1N4148
(D)
50V
100P
(D)
50V
100P
1K
(D)
50V
100P
100U
10K
27K
3.3K
100V
0.01U
(EPI)
56K
5.1V
A733
100
100
100
100
2.2K
4.7K
10K
(EPI)
100V
0.0022U
16V
1000U
(EL)
LM7812
100V
8200P
(EPI)
100V
0.15U
(EPI)
100V
0.01U
(EPI)
100V
0.1U
(EPI)
100V
0.0082U
(EPI)
1K
1%
4.75K
(H-SIZE)
3K
10K
50V
(OPEN)
(D)
TDA4856
105C
16V
1000U
(EL)
698
(1%)
22.1K
(1%)
2.61K
(1%)
100V
0.1U
(EPI)
+12V
HCLAMP
VOUT1
VOUT2
AFC
BDRV
VFOCUS
HDRV
BOP
+17VA
VS
SCL
SDA
HS
FIGURE.5 99sl Autosync Deflection Controller circuit
The autosync deflection controller circuit is shown in FIGURE.5. R3924 and R3925 is set fhmax and
fhmin of the horizontal oscillator, which make 99sl monitor that have 28.5KHz free run mode and
horizontal hold frequency range are from 30KHz to 98KHz.
2.1.5 99sl Vertical Output Circuit
+
VI(FBK)
VO(GUARD)
9
8
VO(A)
VFB
7
6
GND VO(B)
VP I2(DRIVE)
I1(DRIVE)
5
4
3
2
1
4
3
+
+
R215
R211
RF208
R210
R216
C214
R207
R205
RF209
C201
IC201
C208
VDY
C205
D201
D202
C207
C202
TR201
Q255
R203
R201
C203
C204
ZD201
ZD202
R202
C210
C209
20
1.5K
(MOF)
2W
1.5K
1.5K
3.9K
(PE)
100V
0.1U
1W
0.56
2W
82
(FUS)
1/2W
250V
0.47U
(EL)
(HS:34.74507.001)
TDA8351
(D)
50V
0.1U
(D)
50V
2200P
1N4148
1N4148
100V
0.1U
(PE)
100V
0.01U
(PE)
100
BF422
5.6K
6.8K
100V
22U
(EL)
25V
2200U
(EL)
1W
24V
1W
24V
3.9K
50V
1000P
(D)
50V
1000P
(D)
VOUT1
VOUT2
V-BLANK
VBLANK
G1
+24V
+16V
+80V
0.22
FIGURE.6 99sl Vertical Output Circuit
TDA8351 vertical deflection booster is proper for TDA4854 autosync deflection IC. This vertical
output circuit is shown in FIGURE.6. This vertical driver IC circuit is a bridge configuration. From
TDA4854 differential output signal V-OUT1 and V-OUT2 connected to TDA8351 pin1 and pin2 via DC-
couple. The vertical deflection coil is connected between the output amplifier (pin4 and pin7), which are
driven in opposite phase. The TDA8351 can output current 2.8Ap-p maximum to drive V-DY(Vertical
Deflection Yoke). It can be calculated by:
Содержание 7299sl
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