PCIe-COM-8SM / -4SM User Manual
15
To ensure the proper operation of the Baud Rate Generator, users should avoid setting the
value „0‟ to Sample Clock, Divisor and Prescaler.
The following table lists some of the commonly used Baud Rates and the register settings that
generate a specific Baud Rate. The examples assume an Input Clock frequency of 14.7456
Mhz. The SCR register is
set to „0h‟, and the CPRM and CPRN registers are set to „1h‟ and
„0h‟ respectively. In these examples, the Baud Rates can be generated by different
combination of the DLH and DLL register values.
Baud Rate DLH DLL
1,200
3h
00h
2,400
1h
80h
4,800
0h
C0h
9,600
0h
60h
19,200
0h
30h
28,800
0h
20h
38,400
0h
18h
57,600
0h
10h
115,200
0h
08h
921,600
0h
01h
Table 5-2: Sample Baud Rate Setting
W
e re-define the parameter of "Baudrate" on DCB structure,
Bit[30:28]: User Defined Baudrate, this value has to be non-zero
Bit[27:24]: to indicate the value of SCR (SampleClock)
Bit[23:16]: to indicate the value to put in DLH
Bit[15:8]: to indicate the value to put in DLL
Bit[7:3]: to indicate the value to put in M (CPRM)
Bit[2:0]: to indicate the value to put in N (CPRN)
If you want to set
DLL=1
DLH=0
SCR=12
then, the parameters of Baudrate in the DCB structure should be set to 0x1c000108. When
the driver finds the parameter "Baudrate" does not exist on the default baudrate table, and Bit
28 is set to "1", it will get the values of SCR, DLL, DLH, M and N from the Baudrate parameter
and set to the registers directly.
