Manual PCI-DIO-48JP/JPS
5
Chapter 1: Functional Description
FEATURES
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48 Bits of Digital Input/Output.
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Interrupt Generation on Input or under program control (Model “48JP”)
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Change-of-state Interrupt Software Enabled in Six 8-Input Ports.(Model “48JPS”)
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All 48 I/O Lines Buffered on the Board.
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I/O Buffers Can Be Enabled/Disabled under Program Control
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Four and Eight Bit Ports Independently Selectable for I/O.
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Pull-Ups on I/O Lines.
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Resettable Fused +5V Supply Available to the User.
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High Density 68-Pin SCSI Pin-In-Socket Connector
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Signal Level Compatible with Industry Standard I/O Racks like Gordos, Opto-22, Potter &
Brumfield, Western Reserve Controls, etc.
APPLICATIONS
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Automatic Test Systems.
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Laboratory
Automation.
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Robotics
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Machine
Control.
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Security Systems, Energy Management.
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Relay Monitoring and Control.
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Parallel Data Transfer to/from the PC.
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Sensing Switch Closures or TTL, DTL, CMOS Logic
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Driving Indicator Lights or Recorders
DESCRIPTION
These PCI bus cards provide 48 bits of parallel digital input/output capability and can be installed in seven-
inch (178 mm) or longer PCI-bus slots. Each I/O line is buffered and capable of sourcing 15 mA or sinking
24 mA (64 mA on request). The cards contain two type 8255 Programmable Peripheral Interface chips
(PPI) to provide computer interface to 48 lines. Each PPI provides three 8-bit ports A, B, and C. Each 8-bit
port can be software configured to function either as inputs or as latched outputs. Port C can also be
software configured for four inputs and four latched outputs. Pull-ups on the cards assure that there are no
erroneous outputs at power-up until the card is initialized by system software.
The feature that distinguishes the “48JPS” model from the “48JP" card is that the state of all inputs can be
monitored and, if one or more bits change state, a latched interrupt request can be generated. Thus, it is
not necessary to use software to continuously poll the inputs to detect a change of state. The change-of-
state interrupt is enabled by a software write to an interrupt-enable register. Six bits in that register control
six eight-bit input ports. The change-of-state interrupt latch can be cleared by a software write.
Also, Port C bit 3 at each 24-bit group can be used as an external interrupt to the computer if the IEN
jumpers are installed. When Port C bit 3 goes high (edge triggering) when interrupts are enabled, an
interrupt is generated. Interrupts from the ports are OR'ed together and OR'ed with the change-of-state
interrupt. Interrupt levels are assigned by the system.
Tristate I/O line buffers (74LS245) are configured automatically by hardware logic for input or output
according to the direction assignment programmed into a control register in the related PPI. Further, if a