ACCES I/O Products, Inc.
MADE IN THE USA
mPCIe-ADIO16-16F Family Manual
10
Rev B1f
enWDG:
SET enWDT to enable the
“
WDT Output Status
”
Digital Output Secondary Function on DIO 11. DIO 11 (I/O Group 4) becomes an output and indicates the state
of the Watchdog Feature.
enEXT:
SET enEXT to enable the
“
External IRQ
”
Digital Input Secondary Function on DIO 13 so the selected edge on the input will (optionally) generate IRQs.
enLDAC:
SET enLDAC to enable the
“
External LDAC
”
Digital Input Secondary Function on DIO12 so the selected edge will cause the DACs to update and optionally
generate an IRQ.
enSTART:
SET enSTART to enable the
“
ADC Start Conversion
”
Digital Input Secondary Function on DIO 14 so the selected edge will cause an ADC Start Event and
optionally generate an IRQ.
enTRIG:
SET enTRIG to enable the “ADC Trigger”
Digital Input Secondary Function on DIO15 so the selected edge will trigger timed ADC conversions and optionally
generate an IRQ. Consult the “Software Tips” section for details on using ADC Trigger.
Each Digital Input Secondary function has a configurable active edge, rising or falling. SET the corresponding edge
XXX
bit to select rising edge, CLEAR the bit for falling edge.
IOG
x
:
SET each IOGx bit to configure the digital I/O bits in the associated I/O Group for use as digital outputs. CLEAR an IOG
x
bit to configure the I/O Group for use as
inputs.
Watchdog Control, 4C of 64-bit Memory BAR[2+3] Read/Write 32-bits only
bit D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Name Watchdog Timeout
Write the number of Ticks (which occur at the ADC Base Clock Rate (+C)) before the Watchdog should timeout (“Bark”); e.g. for
a one-second timeout period write the value read from +C
to +4C.
When the Watchdog Barks the board is RESET as if just powered on (or as if a 1 is written to the Resets and Power (+0) register) with the following exceptions:
If the “WDT Output Status” DIO Secondary Function is enabled then DIO
11 remains an output and asserts 0.
Bit D31 of the IRQ Enable/Clear and Status
(+40) “WDG” is latched SET to indicate that the Watchdog timed out.
Write 0 to the Watchdog Timeout (+4C) register to disable the Watchdog Feature.
In Windows
1
, please consult the various samples (C#, Delphi, and more) to explore how to program the device. The AIOAIO Software Reference Manual.pdf provides reference material
covering all AIOAIO Library APIs. A quick reference of the most-applicable functions is provided, below:
Under certain circumstances the following information might prove useful:
A NOTE ABOUT PERFORMANCE
The PCI Express bus and the PCI Express Mini Card standard are capable of very high bandwidth, but the latency per-transaction is roughly the same as all the other busses
–
it hasn’t
improved in decades. This means you can expect to usually see a not-less-than 1MHz transaction rate. Typical rates exceed 3MHz [0.3µs].
Unfortunately, modern Operating Systems have introduced a new source of latency, the kernel / userland division. Application code runs in userland, which must transition to the kernel
in order to perform any hardware operation. This transition adds quite a lot of latency, which varies between different OSes, motherboards and revisions thereof, etcetera. A Windows
XP system can see an additional 7µs per transaction; a modern computer might see 3µs or less. Any transaction from the kernel itself, however, avoids this additional overhead.
Real-time operating systems will enable the highest transaction rates possible, all the way up to the hardware limits.
1
In Linux or OSX please refer to the documentation at
