ACCES I/O Products, Inc.
MADE IN THE USA
mPCIe- and M.2-AIO16-16F Family Manual
6
Rev B6e
REGISTER DETAILS
Register bits labeled UNUSED or RSV are reserved and should be cleared to zero in all write operations and ignored in all read operations.
Resets and Power, 0 of 64-bit Memory BAR[2+3] Read/Write 32-bits only
bit D31 THROUGH D7
D6
D5
D4
D3
D2
D1
D0
Name UNUSED
RST FIFO
RST DIO
UNUSED
RST DAC
PD ADC
RST ADC
RST BOARD
RST FIFO:
Writing with bit D6 set will reset the ADC FIFO, returning it to the power-on / reset state: emptying the FIFO by throwing away the contents.
RST DIO:
Writing with bit D5 set will reset the Digital I/O circuits to their power-on / reset state: returning all I/O Groups to input mode and disabling secondary
functions.
RST DAC:
Writing with bit D3 set will reset the Analog Output circuits to their power-on / reset state: ±10V range on all DAC outputs with 0V on each output.
PD ADC:
Writing a 1 will power the ADAS3022 down. Write a 0 to power the ADAS3022 back up. Only this bit does not auto-clear to zero on write.
RST ADC:
Writing a 1 will reset the Analog Input circuits to their power-on / reset state: see each ADC Register for more details
RST BOARD:
Writing a 1 will reset the entire device to its power-on / reset state.
All RST bits are “command” bits: a 1 causes the reset to occur, and the reset clears the 1.
DAC Control, 4 of 32-bit Memory BAR[1]Read/Write 32-bits only
bit D31 through D24
D23 through D20
D19 through D16
D15 through D0
Name UNUSED
C3 C2
C1
C0
A3 A2 A1 A0 16-bit DAC Counts (0-FFFF)
Please refer to the LTC2664 Data Sheet for details.
Consult the AIOAIO Software Reference, or our sample
programs’ source, to avoid the hassle:
DAC_SetRange1(iBoard, iChannel, iRange);
DAC_OutputV(iBoard, iChannel, double Voltage);
ADC Base Clock, C of 32-bit Memory BAR[1]Read Only 32-bits only
ADC Base Clock: Reading this 32-bit register returns the speed (in Hertz) of the clock used to generate ADC Start Conversions. Typical value is 50Million (50MHz), but for
broadest compatibility software should always read this register during init, and always use the read value when calculating what, if any, divisor to write to the
ADC Rate Divisor register.
ADC Rate Divisor, 10 of 32-bit Memory BAR[1]Read/Write 32-bits only
ADC Rate Divisor: Write a 32-bit divisor to the ADC Rate Divisor register to control the speed at which ADC Conversions occur in selected ADC Conversion Start Modes.
Actual ADC Start Rate (Hz) = ADC Base Clock ÷ ADC Rate Divisor
ADC Rate Divisor = integer(ADC Base Clock ÷ Target ADC Start Rate)
In ADC Scan Start mode each timeout of the +10 divisor begins a scan of channels. In all other modes the +10 rate selects the conversion rate per-channel.
ADC Rate Divisor #2, 14 of 64-bit Memory BAR[2+3] Read/Write 32-bits only
ADC Rate Divisor #2:
Write a 32-bit divisor to the ADC Rate Divisor #2 register to control the speed at which ADC Conversions occur within each scan when running in ADC
Scan Start Modes.
In “ADC Scan” start modes only, one Scan of ADC CH0 through the channel selected in +38 INx2:0 bits occurs at the rate select
ed at +10. During each Scan the first channel is
converted immediately, and subsequent channels are acquired at the rate selected at +14.
