191
MC96F6432S
ABOV Semiconductor Co., Ltd.
11.12.10.5
USIn Asynchronous Data Reception
To receive asynchronous data frame, the UART includes a clock and data recovery unit. Theclock recovery logic is
used for synchronizing the internally generated baud-rate clock to the incoming asynchronous serial frame on the
RXDn pin.
The data recovery logic does sampling and low pass filtering the incoming bits, and removing the noise of RXDn pin.
The next figure illustrates the sampling process of the start bit of an incoming frame. The sampling rate is 16 times of
the baud-rate in normal mode and 8 times the baud-rate for double speed mode (DBLSn=1). The horizontal arrows
show the synchronization variation due to the asynchronous sampling process. Note that larger time variation is
shown when using the double speed mode.
Figure 11.61
Asynchronous Start Bit Sampling (USIn)
RXDn
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
IDLE
BIT0
START
0
1
2
3
4
5
6
7
8
1
2
Sample
(DBLSn = 0)
Sample
(DBLSn = 1)
Содержание MC96F6332SD
Страница 15: ...15 MC96F6432S ABOV Semiconductor Co Ltd 4 Package Diagram Figure 4 1 44 Pin MQFP Package...
Страница 16: ...16 MC96F6432S ABOV Semiconductor Co Ltd Figure 4 2 32 Pin LQFP Package...
Страница 17: ...17 MC96F6432S ABOV Semiconductor Co Ltd Figure 4 3 32 Pin SOP Package...
Страница 18: ...18 MC96F6432S ABOV Semiconductor Co Ltd Figure 4 4 28 Pin SOP Package...
Страница 19: ...19 MC96F6432S ABOV Semiconductor Co Ltd Figure 4 5 28 Pin TSSOP Package...
