Abov MC95FG208 Series Скачать руководство пользователя

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152

MC95FG308 / MC95FG208

ABOV Semiconductor Co., Ltd.

After doing one of the actions above, write arbitrary value to I2CSR to release SCL line. In case of 1), move to

step 7. In case of 2), move to step 9 to handle STOP interrupt. In case of 3), move to step 6 after transmitting

the data in I2CDR and if transfer direction bit is ‘1’ go to master receiver section.

1-byte of data is being transmitted. During data transfer, bus arbitration continues.

This is ACK signal processing stage for data packet transmitted by master. I2C holds the SCL LOW. When I2C

loses bus mastership while transmitting data arbitrating other masters, the MLOST bit in I2CSR is set. If then,

I2C waits in idle state. When the data in I2CDR is transmitted completely, I2C generates TEND interrupt.

I2C can choose one of the following cases regardless of the reception of ACK signal from slave.

1) Master receives ACK signal from slave, so continues data transfer because slave can receive more data from

master. In this case, load data to transmit to I2CDR.

2) Master stops data transfer even if it receives ACK signal from slave. In this case, set the STOP bit in I2CMR.

3) Master transmits repeated START condition with not checking ACK signal. In this case, load SLA+R/W into

the I2CDR and set the START bit in I2CMR.

After doing one of the actions above, write arbitrary value to I2CSR to release SCL line. In case of 1), move to

step 7. In case of 2), move to step 9 to handle STOP interrupt. In case of 3), move to step 6 after transmitting

the data in I2CDR, and if transfer direction bit is ‘1’ go to master receiver section.

This is the final step for master transmitter function of I2C, handling STOP interrupt. The STOP bit indicates that

data transfer between master and slave is over. To clear I2CSR, write arbitrary value to I2CSR. After this, I2C

enters idle state.

11.9.8.2

Master Receiver

To operate I2C in master receiver, follow the recommended steps below.

Enable I2C by setting IICEN bit in I2CMR. This provides main clock to the peripheral.

Load SLA+R into the I2CDR where SLA is address of slave device and R is transfer direction from the viewpoint

of the master. For master receiver, R is ‘1’. Note that I2CDR is used for both address and data.

Configure baud rate by writing desired value to both I2CSCLLR and I2CSCLHR for the Low and High period of

SCL line.

Configure the I2CSDAHR to decide when SDA changes value from falling edge of SCL. If SDA should change

in the middle of SCL LOW period, load half the value of I2CSCLLR to the I2CSDAHR.

Set the START bit in I2CMR. This transmits a START condition. And also configure how to handle interrupt and

ACK signal. When the START bit is set, 8-bit data in I2CDR is transmitted out according to the baud-rate.

This is ACK signal processing stage for address packet transmitted by master. When 7-bit address and 1-bit

transfer direction is transmitted to target slave device, the master can know whether the slave acknowledged or

not in the 9th high period of SCL. If the master gains bus mastership, I2C generates GCALL interrupt regardless

of the reception of ACK from the slave device. When I2C loses bus mastership during arbitration process, the

MLOST bit in I2CSR is set, and I2C waits in idle state or can be operate as an addressed slave. To operate as a

slave when the MLSOT bit in I2CSR is set, the ACKEN bit in I2CMR must be set and the received 7-bit address

must equal to the SLA bits in I2CSAR. In this case I2C operates as a slave transmitter or a slave receiver (go to

appropriate section). In this stage, I2C holds the SCL LOW. This is because to decide whether I2C continues

Содержание MC95FG208 Series

Страница 1: ...ternal 8MHz RC Oscillator 3 TA 40 85 C Internal 1MHz RING Oscillator Peripheral features 12 bit Analog to Digital Converter 15inputs Serial Interface USART SPI I2C 6 channel 10 bit PWM for Motor Contr...

Страница 2: ...k Diagram 2 3 2011 06 28 Add Port RESET N C 2 4 2011 08 17 Add DC Characteristics 2 5 2011 11 24 Add Appendix B Instructions on how to use the input port 2 6 2011 11 28 Correct 28SOP package diagram 2...

Страница 3: ...e I O 8 16 bit timer counter watchdog timer watch timer SPI USART I2C on chip POR BOD 12 bit A D converter analog comparator buzzer driving port 10 bit high speed PWM output on chip oscillator and clo...

Страница 4: ...High Frequency 10 bit PWM Using Timer1 10 bit PWM Using Timer3 Watch Dog Timer Watch Timer SPI USART 2 ch I2C Buzzer Driving Port 12 bit A D Converter 15 Input channels 32 Pin Analog Comparator On Chi...

Страница 5: ...ich is attached to user s system The OCD can read or change the value of MCU internal memory and I O peripherals And the OCD also controls MCU internal debugging logic it means OCD controls emulation...

Страница 6: ...miconductor Co Ltd 1 3 3 Programmer Single programmer PGMplus USB It programs MCU device directly Figure 1 2 PGMplusUSB Single writer Standalone PGMplus It programs MCU device directly Figure 1 3 Stan...

Страница 7: ...pins DSCL DSDA VDD and VSS for programming reading the flash The MC95FG308 needs only four signal lines including VDD and VSS pins for programming FLASH with serial protocol Therefore the on board pr...

Страница 8: ...T5 P32 INT6 P33 INT7 SPI P00 SS0 P01 SCK0 P02 MOSI0 P03 MISO0 USART0 P00 SS0 P01 ACK0 P02 TxD0 P03 RxD0 USART1 P34 SS1 P35 ACK1 P36 TxD1 P37 RxD1 I2 C P07 P26 SDA P06 P25 SCL On Chip Debug M8051 CORE...

Страница 9: ...AVref P24 AN13 P23 AN12 VSS P22 RESETB P21 XOUT P20 XIN P16 INT3 T3O PWM3 AN9 P37 RxD1 AN11 P36 TxD1 AN10 P35 ACK1 NOTE 1 If 28PKG Pin 7 8 25 and 26 in 32 pin package are removed and their function ca...

Страница 10: ...NT0 P10 PWM1AB INT1 P11 PWM1BA BUZ INT2 P12 P13 T0O PWM1BB P14 EC0 PWM1CA P15 PWM1CB AN8 P34 SS1 P35 ACK1 P36 TxD1 AN10 P37 RxD1 AN11 P16 INT3 T3O PWM3 AN9 P20 XIN P21 XOUT P22 RESETB VSS P23 AN12 P24...

Страница 11: ...0 P10 PWM1AB INT1 P11 PWM1BA BUZ INT2 P12 P13 T0O PWM1BB P14 EC0 PWM1CA P15 PWM1CB AN8 P34 SS1 P35 ACK1 P36 TxD1 AN10 P37 RxD1 AN11 P16 INT3 T3O PWM3 AN9 P20 XIN P21 XOUT P22 RESETB VSS P23 AN12 P24 A...

Страница 12: ...CL ACOUT AN6 T0O SCL P06 DSDA AN7 EC0 SDA P07 VDD PWM1AA T1O INT0 P10 PWM1AB INT1 P11 PWM1BA BUZ INT2 P12 PWM1BB T0O P13 PWM1CA EC0 P14 AN8 PWM1CB P15 SS1 P34 P31 INT5 P30 INT4 P03 RxD0 MISO0 EC2 AN3...

Страница 13: ...I0 T2O AN2 P01 ACK0 SCK0 AN1 P00 SS0 AN0 AVref VSS P22 RESETB P21 XOUT P20 XIN P16 INT3 T3O PWM3 AN9 P15 PWM1CB AN8 Figure 3 5 MC95FG208 20SOP TSSOP pin assignmemt MC95FG208 1 2 3 4 5 6 7 8 SXIN AC AN...

Страница 14: ...14 MC95FG308 MC95FG208 ABOV Semiconductor Co Ltd 4 Package Diagram Figure 4 1 32 Pin SOP Package...

Страница 15: ...15 MC95FG308 MC95FG208 ABOV Semiconductor Co Ltd Figure 4 2 32 Pin QFN Package...

Страница 16: ...16 MC95FG308 MC95FG208 ABOV Semiconductor Co Ltd Figure 4 3 32 Pin LQFP Package...

Страница 17: ...17 MC95FG308 MC95FG208 ABOV Semiconductor Co Ltd Figure 4 4 28 Pin SOP Package...

Страница 18: ...18 MC95FG308 MC95FG208 ABOV Semiconductor Co Ltd Figure 4 5 28 Pin SOP Package continue...

Страница 19: ...19 MC95FG308 MC95FG208 ABOV Semiconductor Co Ltd Figure 4 6 28 Pin SOP Package...

Страница 20: ...20 MC95FG308 MC95FG208 ABOV Semiconductor Co Ltd Figure 4 7 28 Pin TSSOP Package...

Страница 21: ...21 MC95FG308 MC95FG208 ABOV Semiconductor Co Ltd Figure 4 8 20 Pin SOP Package...

Страница 22: ...22 MC95FG308 MC95FG208 ABOV Semiconductor Co Ltd Figure 4 9 20 Pin TSSOP Package...

Страница 23: ...23 MC95FG308 MC95FG208 ABOV Semiconductor Co Ltd Figure 4 10 16 Pin SOP Package...

Страница 24: ...24 MC95FG308 MC95FG208 ABOV Semiconductor Co Ltd Figure 4 11 16 Pin TSSOP Package...

Страница 25: ...e when this port is used as output port AN8 AN9 can be selected by ADCM register Input PWM1AA T1O INT0 P11 PWM1AB INT1 P12 PWM1BA BUZ INT2 P13 PWM1BB P14 PWM1CA P15 AN8 PWM1CB P16 AN9 PWM3 T3O INT3 P2...

Страница 26: ...ABLE LevelShift 1 8V to ExtVDD LevelShift ExtVDD to 1 8V DATA REGISTER OPEN DRAIN REGISTER PULL UP REGISTER SUB FUNC DATA OUTPUT DIRECTION REGISTER SUB FUNC DIRECTION 0 1 MUX MUX 0 1 0 1 MUX r D CP Q...

Страница 27: ...Shift ExtVDD to 1 8V DATA REGISTER OPEN DRAIN REGISTER PULL UP REGISTER SUB FUNC DATA OUTPUT DIRECTION REGISTER SUB FUNC DIRECTION 0 1 MUX MUX 0 1 0 1 MUX r D CP Q DEBOUNCE CLK DEBOUNCE ENABLE PORTx I...

Страница 28: ...ent damage to the device This is a stress rating only and functional operation of the device at any other conditions beyond those indicated in the operational sections of this specification is not imp...

Страница 29: ...V Analog Input Current IAIN VDD Vref 5V 10 uA Analog Block Current IAVDD VDD Vref 5V VDD Vref 3V 1 0 5 3 1 5 mA VDD Vref 5V Power down mode 100 500 nA BGR VDD 5V TA 25 1 67 V VDD 4V TA 25 1 63 VDD 3V...

Страница 30: ...AN2 STOP to RUN 200 us Table 7 5 Voltage Dropout Converter Characteristics NOTE 1 STOP1 WDT running STOP2 WDT disable 7 6 Power On Reset Characteristics Parameter Symbol Condition MIN TYP MAX Unit Ope...

Страница 31: ...Oscillator Characteristics Parameter Symbol Condition MIN TYP MAX Unit Operating Voltage 1 8 5 5 V Operating Temperature 40 85 Frequency 1 MHz Stabilization Time ms Operating Current IDD uA SIDD 1 uA...

Страница 32: ...IIH ALL PAD 1 uA Input Low Leakage Current IIL ALL PAD 1 uA Pull Up Resister RPU ALL PAD 20 50 k Power Supply Current IDD1 Run Mode fXIN 12MHz 5V 2 6 10 mA IDD2 Sleep Mode fXIN 12MHz 5V 1 5 5 mA IDD3...

Страница 33: ...ernal Clock Transition Time tRCP tFCP XIN 10 ns External Interrupt Input Width tIW INT0 INTx 2 tSYS External Interrupt Transition Time tFI tRI INT0 INTx 1 us nRESET Input Pulse L Width tRST nRESET 8 t...

Страница 34: ...H or L Pulse Width tSCKL tSCKH SCK tSYS 30 ns Output Clock Pulse Transition Time tFSCK tRSCK SCK 30 ns First Output Clock Delays Time tFOD OUTPUT Output Clock Delay Time tDS OUTPUT 100 ns Input Pulse...

Страница 35: ...y 12Mhz Ext Load Cap 5pF 22pF 35pF C1 C2 Table 7 14 Main Clock Oscillator Characteristics XIN XOUT C1 C2 Figure 7 3 Crystal Oscillator 7 15 Sub Clock Oscillator Characteristics VDD 5 0V 10 VSS 0V TA 4...

Страница 36: ...ting range e g outside specified VDD range This is for information only and devices are guaranteed to operate properly only within the specified range The data presented in this section is a statistic...

Страница 37: ...am counter is capable of addressing up to 64Kbytes but this device has just 8Kbytes program memory space Figure 8 1 shows a map of the lower part of the program memory After reset the CPU begins execu...

Страница 38: ...5FG208 ABOV Semiconductor Co Ltd Figure 8 1 Program Memory User Function Mode 8Kbytes Included Interrupt Vector Region Non volatile and reprogramming memory Flash memory based on EEPROM cell FFFFH 1FF...

Страница 39: ...ce occupying the same block of addresses 80H through FFH although they are physically separate entities The lower 128bytes of RAM are present in all 8051 devices as mapped in Figure 8 3 The lowest 32b...

Страница 40: ...5E 5D 5C 5B 5A 59 58 57 56 55 54 53 52 51 50 4F 4E 4D 4C 4B 4A 49 48 47 46 45 44 43 42 41 40 3F 3E 3D 3C 3B 3A 39 38 37 36 35 34 33 32 31 30 2F 2E 2D 2C 2B 2A 29 28 27 26 25 24 23 22 21 20 1F 1E 1D 1...

Страница 41: ...2bytes EEPROM Data memory This area has no relation with RAM FLASH It can read and write through SFR with 8 bit unit For more information about EEPROM Data memory see chapter 15 Figure 8 4 XDATA Memor...

Страница 42: ...CTRL2 UCTRL3 USTAT UBAUD UDATA D8H I2CMR I2CSR I2CSCLLR I2CSCLHR I2CSDHR I2CDR D0H PSW SPICR SPIDR SPISR T4H I2CSAR1 I2CSAR C8H T3CR T3DR PWM3PR T3 PWM3DR CDR3 PWM3HR T4CR T4L C0H T2DLYB T1DLYC T1ISR...

Страница 43: ...R W R W R W R W R W R W R W R W Initial value 00H B B Register SP Stack Pointer 81H 7 6 5 4 3 2 1 0 SP R W R W R W R W R W R W R W R W Initial value 07H SP Stack Pointer DPL Data Pointer Low Byte 82H...

Страница 44: ...lag F1 User Definable Flag P Parity Flag Set cleared by hardware each instruction cycle to indicate an odd even number of 1 bits in the accumulator EO Extended Operation Register A2H 7 6 5 4 3 2 1 0 T...

Страница 45: ...cleared in this read write register will select the corresponding pin in Px to become an input setting a bit sets the pin to output All bits are cleared by a system reset 9 2 3 Pull up Resistor Select...

Страница 46: ...en drain Selection Register P0DB 2F18H R W 00H P0 Debounce Enable Register PCI0 AEH R W 00H P0 Pin Change Interrupt Enable Register P1 88H R W 00H P1 Data Register P1IO 91H R W 00H P1 Direction Regist...

Страница 47: ...00H Px 7 0 I O Data PxIO Px Direction Register 89H 91H 99H A1H 7 6 5 4 3 2 1 0 Px7IO Px6IO Px5IO Px4IO Px3IO Px2IO Px1IO Px0IO R W R W R W R W R W R W R W R W Initial value 00H PxIO 7 0 Px data I O d...

Страница 48: ...rupt of P0 port 0 Disable 1 Enable PSR0 Port Selection Register 2F50H 7 6 5 4 3 2 1 0 PSR07 PSR06 PSR05 PSR04 PSR03 PSR02 PSR01 PSR00 R W R W R W R W R W R W R W R W Initial value 00H PSR0 7 0 P07 P00...

Страница 49: ...T0O ports selection register 0 P0 3 2 for RxD0 TxD0 default P0 7 6 for EC0 T0O 1 P3 3 2 for RxD0 TxD0 P1 4 3 for EC0 T0O 9 4 Port RESET Noise Canceller The Figure 9 1 is the Noise canceller diagram fo...

Страница 50: ...through the other bits of the interrupt enable registers The MC95FG308 supports a four level priority scheme Each maskable interrupt is individually assigned to one of four priority levels by writing...

Страница 51: ...gister as shown in Figure 10 1 Also each external interrupt source has control setting bits The EIFLAG External interrupt flag register register provides the status of external interrupts EIBOTH EIEDG...

Страница 52: ...PI I2 C FLAG6 FLAG7 IE5 ADH INT6 0 1 2 3 4 5 6 7 8 9 10 11 30 31 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 6 7 8 9 10 11 6 7 8 9 10 11 6 7 8 9 10 11 30 31 30 31 30 31 Release Stop Sleep EA IE 7 A8H EIEDGE A...

Страница 53: ...1 IE1 5 12 Maskable 005BH T0 INT12 IE2 0 13 Maskable 0063H T1 INT13 IE2 1 14 Maskable 006BH T2 INT14 IE2 2 15 Maskable 0073H T3 INT15 IE2 3 16 Maskable 007BH T4 INT16 IE2 4 17 Maskable 0083H EEPROM IN...

Страница 54: ...struction to go interrupt service routine needs 5 8 machine cycle and the interrupt service task is terminated upon execution of an interrupt return instruction RETI After generating interrupt to go t...

Страница 55: ...rough software for special features is possible Figure 10 5 Execution of Multi Interrupt Following example is shown to service INT0 routine during INT1 routine in Figure 10 6 In this example INT0 inte...

Страница 56: ...t Enable Accept Timing Figure 10 6 Interrupt Response Timing Diagram 10 9 Interrupt Service Routine Address Figure 10 7 Correspondence between Vector Table Address and the Entry Address of ISR 02H 01H...

Страница 57: ...pling interrupt source it is decided to low 8 bit of interrupt vector M8051W core makes interrupt acknowledge at first cycle of command executes long call to jump interrupt routine as INT_VEC CLP2 CLP...

Страница 58: ...t generating condition is satisfied The flag is cleared when the interrupt routine is executed Alternatively the flag can be cleared by writing a 0 to it 10 12 4 External Interrupt Edge Register EIEDG...

Страница 59: ...Edge Register EIPOLA A6H R W 00H External Interrupt Polarity Register EIBOTH A7H R W 00H External Interrupt Both Edge Enable Register Table 10 3 Register Map 10 13 Interrupt Register Description The...

Страница 60: ...disable all interrupt bits 0 All Interrupt disable 1 All Interrupt enable INT5E Reserved 0 Disable 1 Enable INT4E Enable or disable Pin Change Interrupt 0 Port 0 0 Disable 1 Enable INT3E Enable or di...

Страница 61: ...E Enable or disable USART0 Tx Interrupt 0 Disable 1 Enable INT6E Enable or disable USART0 Rx Interrupt 0 Disable 1 Enable IE2 Interrupt Enable Register 2 AAH 7 6 5 4 3 2 1 0 INT17E INT16E INT15E INT14...

Страница 62: ...Interrupt 0 Disable 1 Enable INT19E Enable or disable Analog Comparator Interrupt 0 Disable 1 Enable INT18E Enable or disable ADC Interrupt 0 Disable 1 Enable IE4 Interrupt Enable Register 4 ACH 7 6 5...

Страница 63: ...1E Enable or disable External Interrupt 7 0 Disable 1 Enable INT30E Enable or disable External Interrupt 6 0 Disable 1 enable IP Interrupt Priority Register B8H 7 6 5 4 3 2 1 0 IP7 IP6 IP5 IP4 IP3 IP2...

Страница 64: ...POLA External Interrupt Polarity Register A6H 7 6 5 4 3 2 1 0 POLA7 POLA6 POLA5 POLA4 POLA3 POLA2 POLA1 POLA0 R W R W R W R W R W R W R W R W Initial value 00H POLA 7 0 According to EIEDGE External in...

Страница 65: ...ister A7H 7 6 5 4 3 2 1 0 BOTH7 BOTH6 BOTH5 BOTH4 BOTH3 BOTH2 BOTH1 BOTH0 R W R W R W R W R W R W R W R W Initial value 00H BOTH 7 0 Determines which type of interrupt may occur EIBOTH or EIEDGE EIPOL...

Страница 66: ...l clock signal into the XIN pin and open the XOUT pin The default system clock is INT RC Oscillator and the default division rate is one In order to stabilize system internally use 1MHz RING oscillato...

Страница 67: ...on rate come into effect NOTE To change by software CBYS set to 1 DIV1 DIV0 description 0 0 fINTRC 1 8MHz 0 1 fINTRC 2 4MHz 1 0 fINTRC 4 2MHz 1 1 fINTRC 8 1MHz CBYS Control the scheme of clock change...

Страница 68: ...68 MC95FG308 MC95FG208 ABOV Semiconductor Co Ltd 0 0 fINTRC INTRC 8MHz 0 1 fXIN Main Clock 1 16MHz 1 0 fSUB 32 768kHz 1 1 fRING 125kHz...

Страница 69: ...T gives a stable clock generation time On exiting Stop mode BIT gives a stable clock generation time As clock function time interrupt occurrence 11 2 2 Block Diagram RING OSC 1MHz BITR 8 bit COUNT BIT...

Страница 70: ...F BCLR BCK2 BCK1 BCK0 R W R R R R W R W R W R W Initial value 05H BITF When BIT Interrupt occurs this bit becomes 1 For clearing bit write 0 to this bit 0 no generation 1 generation BCLR If BCLR bit i...

Страница 71: ...sts of 8 bit binary counter and the watchdog timer data register When the value of 8 bit binary counter is equal to the 8 bits of WDTR the interrupt request flag is generated This can be used as Watch...

Страница 72: ...oper operation the data should be greater than 01H WDTCR Watch Dog Timer Counter Register Read Case 8EH 7 6 5 4 3 2 1 0 WDTCR7 WDTCR6 WDTCR5 WDTCR4 WDTCR3 WDTCR2 WDTCR1 WDTCR0 R R R R R R R R Initial...

Страница 73: ...o Ltd 11 3 6 WDT Interrupt Timing Waveform Figure 11 4 WDT Interrupt Timing Waveform Source Clock BIT Overflow WDTCR 7 0 WDTR 7 0 WDTIF Interrupt WDTRESETB WDTCL Occur WDTR 0000_0011b Match Detect Cou...

Страница 74: ...rcuits may be composed of 21 bit counter which is low 14 bit with binary counter and high 7 bit with auto reload counter in order to raise resolution In WTR it can control WT clear and set Interval va...

Страница 75: ...9DH 7 6 5 4 3 2 1 0 WTEN WTIFR WTIN1 WTIN0 WTCK1 WTCK0 R W R W R W R W R W R W Initial value 00H WTEN Control Watch Timer 0 disable 1 enable WTIFR When WT Interrupt occurs this bit becomes 1 For clea...

Страница 76: ...WTCL Clear WT Counter 0 Free Run 1 Clear WT Counter auto clear after 1 Cycle WTR 6 0 Set WT period WT Interrupt Interval fwck 2 14 x 7bit WT Value 1 NOTE 1 To guarantee proper operation it is greater...

Страница 77: ...y clock select logic which is controlled by the clock select T0CK 2 0 T1CK 3 0 Also the timer PWM event counter 1 can use more clock sources than timer event counter 0 TIMER0 clock source fX 2 4 8 32...

Страница 78: ...ively identical in Timer 0 1 the interrupt of Timer 0 1 occurs The external clock EC0 counts up the timer at the rising edge If EC0 is selected from T0CK 2 0 EC0 port becomes input port The timer 1 ca...

Страница 79: ...rrupt Occur Interrupt Occur Interrupt Clear Start Disable Enable Up count T0ST T1ST Start Stop T0ST T1ST 0 T0CN T1CN Control count T0ST T1ST 1 T0ST T1ST 1 T0CN T1CN 0 T0CN T1CN 1 T0CN T1CN 1 T0DR T1DR...

Страница 80: ...the interrupt occurs at T0 T1 and T0DR T1DR matching time respectively The capture result is loaded into CDR0 CDR1 The T0 T1 value is automatically cleared by hardware and restarts counter This timer...

Страница 81: ...INITIAL VALUE 0000_0000B 2048 512 128 P r e s c a l e r MUX 2 4 8 32 EC0 fx MUX 2 4 8 B3H INT0IF INT0 Interrupt 8 bit Timer0 Counter T0 8 bit 8 bit Timer0 Data Register T0CN Clear B3H T0ST T0CK 2 0 3...

Страница 82: ...ow in Capture Mode T0 T1 Value Interrupt Request INT0F INT1F TIME 1 2 3 4 5 6 n 2 n 1 n Interrupt Interval Period 0 Count Pulse Period PCP Up count CDR0 CDR1 Load Ext INT0 1 PIN T0 T1 Value Interrupt...

Страница 83: ...e 11 13 16 bit Capture Mode of Timer 0 1 16BIT CAP1 T1CN T1ST T1CK3 T1CK2 T1CK1 T1CK0 T0EN T0PE CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST T1CR T0CR 1 X 1 X X X X X 1 1 X X 1 1 1 1 ADDRESS B2H INITIAL VALUE 000...

Страница 84: ...HR 7 6 T1ADR X Source Clock NOTE 1 T1PPR must be set to higher than T1PDR for guaranteeing operation Resolution Frequency T1CK 3 0 0001 250ns T1CK 3 0 0010 500ns T1CK 3 0 0100 2us 10 bit 3 9kHz 1 95kH...

Страница 85: ...r Comparator T1PPR 8 bit 2 bit T1 8 bit B5H B6H T1PHR 1 0 PWM Output Control A Ch PWM Delay Control A Ch T1ADR 8 bit T1PHR 7 6 Comparator B6H T1BDR 8 bit T1PHR 5 4 Comparator BCH PWM Output Control B...

Страница 86: ...Register 8 bit Timer1 Counter 2 bit Clear Comparator T1PPR 8 bit 2 bit T1 8 bit B5H B6H T1PHR 1 0 PWM Output Control A Ch PWM Delay Control A Ch T1ADR 8 bit T1PHR 7 6 Comparator B6H PWM Output Control...

Страница 87: ...rnal clock synchronization circuit So the update data is written before 3 cycle of timer clock to get the right output waveform T1 00 01 02 03 04 P10 PWM POLA 1 T1CR 1 0 10H 2us T1PHR 00H T1PPR 0EH T1...

Страница 88: ...re 11 19 Example of PWM waveform in Back to Back mode at 4Mhz T1 00 01 02 03 04 P10 PWM POLA 1 T1CR 1 0 10H 2us T1PHR 00H T1PPR 0BH T1ADR 05H 09 08 07 06 05 0A 0B 0B 0A 06 07 08 09 02 03 04 05 01 00 0...

Страница 89: ...ssible to stop PWM operation by the software During PHLT bit being 1 PWM output becomes a reset value and internal counter becomes reset as 0 Without changing PWM setting temporarily it is able to sto...

Страница 90: ...s noted that the inversion outputs of A B C channel have the same A ch output waveform According to POLA B C it is able to control the inversion of outputs Figure 11 22 Example of Force Drive All ch w...

Страница 91: ...egister a B BB output of the B channel duty register a C CB output of the C channel duty register are controlled respectively If the UALL bit is set to 1 it is updated B C channel duty at the same tim...

Страница 92: ...wanted channel direction of the 6 channel outputs In the FORCE mode the channel direction of the disabled output is determined by each port control register bit regardless of the PWM stop Figure 11 24...

Страница 93: ...BDH INITIAL VALUE 0000_0000B PWMA PWMAO PWMAO T1_PE POLA POLB POLC POCO N HCKE PLLPD B T1PCR3 X 1 X X X X X X ADDRESS BEH INITIAL VALUE 0000_00 0B DLYA3 DLYA2 DLYA1 DLYA0 DLYAB3 DLYAB2 DLYAB1 DLYAB0...

Страница 94: ...egister T1DR B5H W FFH Timer 1 Data Register T1PPR B5H W FFH Timer 1 PWM Period Register T1 B6H R 00H Timer 1 Register T1ADR B6H R W 7FH Timer 1 PWM 1A Duty Register CDR1 B6H R 00H Capture 1 Data Regi...

Страница 95: ...PWM1 Non Overlap Delay Register ch C CB T1DLYC Timer 1 Interrupt Status Register T1ISR Timer 1 Interrupt Mask Register T1IMSK and PLL Control Register PLLCR 11 5 1 10 Register description for Timer Co...

Страница 96: ...Initial value 00H CDR0 7 0 T0 Capture T1CR Timer 1 Mode Count Register B4H 7 6 5 4 3 2 1 0 16BIT CAP1 T1CN T1ST T1CK3 T1CK2 T1CK1 T1CK0 R W R W R W R W R W R W R W R W Initial value 00H 16BIT Select...

Страница 97: ...ode only B5H 7 6 5 4 3 2 1 0 T1PP7 T1PP6 T1PP5 T1PP4 T1PP3 T1PP2 T1PP1 T1PP0 W W W W W W W W Initial value FFH T1PP 7 0 T1 PWM period T1 Timer 1 Register Read Case B6H 7 6 5 4 3 2 1 0 T17 T16 T15 T14...

Страница 98: ...ing with BLNKB P16 BMOD Control Back To Back Mode operation 0 BtB mode disable only up count 1 BtB mode enable Up Down count PHLT Control PWM 0 PWM running 1 PWM stop UPDT Determine the update time of...

Страница 99: ...CD7 PCD6 PCD5 PCD4 PCD3 PCD2 PCD1 PCD0 R W R W R W R W R W R W R W R W Initial value 7FH T1CDR 7 0 PWM 1C ch Duty NOTE only write when PWM1E 1 T1PHR Timer 1 PWM High Register BCH 7 6 5 4 3 2 1 0 ADR9...

Страница 100: ...t disable 1 P1C or P1CB output enable T1PCR3 Timer 1 PWM Control Register 3 BEH 7 6 5 4 3 2 1 0 T1_PE POLA POLB POLC POCON HCKE PLLPDB R W R W R W R W R W R W R W Initial value 00H T1_PE Control Timer...

Страница 101: ...erlap Delay Register for channel B BB C2H 7 6 5 4 3 2 1 0 DLYB3 DLYB2 DLYB1 DLYB0 DLYBB3 DLYBB2 DLYBB1 DLYBB0 R W R W R W R W R W R W R W R W Initial value 00H DLYB 3 0 PWM B channel Output Delay Risi...

Страница 102: ...this bit 0 Timer Bottom no occurrence 1 Timer Bottom occurrence ICMA PWM A ch Duty Match interrupt status Note for clear write 1 to this bit 0 PWM A ch Duty Match no occurrence 1 PWM A ch Duty Match...

Страница 103: ...able 1 Timer Bottom interrupt enable CMAMSK Control Timer Compare Match or PWM A ch Match interrupt 0 Timer Compare Match or PWM A ch Match interrupt disable 1 Timer Compare Match or PWM A ch Match in...

Страница 104: ...fvco M PLLCT3 PLLCT2 PLLCT1 description 0 0 0 M 1 0 0 1 M 2 0 1 0 M 4 0 1 1 M 5 1 0 0 M 6 1 0 1 M 8 1 1 0 M 10 1 1 1 M 16 PLLCT 0 PLL enable this bit should enable before 1ms for using PLL 0 PLL disa...

Страница 105: ...lock source is selected by clock select logic which is controlled by the clock select T2CK 2 0 T3CK 1 0 TIMER2 clock source fX 1 2 4 64 256 1024 4096 EC2 TIMER3 clock source fX 1 2 16 T2CK In the capt...

Страница 106: ...espectively identical in Timer 2 3 the interrupt of timer T2 3 occurs The external clock EC2 counts up the timer at the rising edge If EC2 is selected from T2CK 2 0 EC2 port becomes input port The tim...

Страница 107: ...Interrupt Occur Interrupt Occur Interrupt Clear Start Disable Enable Up count T2ST T3ST Start Stop T2ST T3ST 0 T2CN T3CN Control count T2ST T3ST 1 T2ST T3ST 1 T2CN T3CN 0 T2CN T3CN 1 T2CN T3CN 1 T2DR...

Страница 108: ...and the interrupt occurs at T 2 3 and T2DR T3DR matching time respectively The capture result is loaded into CDR2 CDR3 The T2 T3 value is automatically cleared by hardware and restarts counter This ti...

Страница 109: ...3CK 1 0 2 INT2 EIEDGE 2 CBH INT3IF INT3 Interrupt 8 bit Timer3 Counter T3 8 bit 8 bit Timer3 Data Register T3CN Clear CCH T3ST INT3 EIEDGE 3 POL3 16BIT PWM3E CAP3 T3CK1 T3CK0 T3CN T3ST T2EN T2PE CAP2...

Страница 110: ...in Capture Mode T2 T3 Interrupt Request INT2F INT3F XXH Interrupt Interval Period FFH 01H FFH 01H YYH 01H Ext INT2 3 PIN Interrupt Request T2IF T3IF FFH FFH YYH 00H 00H 00H 00H 00H T2 T3 Value Interr...

Страница 111: ...PWM period register T3PWHR 3 2 T3PWHR 1 0 PWM Period T3PWHR 3 2 T3PPR X Source Clock PWM Duty T3PWHR 1 0 T3PDR X Source Clock Resolution Frequency T3CK 1 0 00 125ns T3CK 1 0 01 250ns T3CK 1 0 10 2us...

Страница 112: ...PWM output is not retain high or low but toggle Figure 11 34 PWM Mode P r e s c a l e r MUX T2 Clock Source fx T3CN T3ST T3CK 1 0 2 1 2 16 8 bit Timer3 PWM Period Register 8 bit Timer3 Counter 2 bit C...

Страница 113: ...n the T3PWHR register must set to 1 T3 00 01 02 03 04 T3 PWM POL 1 T3CR 1 0 10H 2us T3PWHR 00H T3PPR 0EH T3PDR 05H 09 08 07 06 05 0D 0C 0B 0A 02 01 00 0E 06 05 04 03 0A 09 08 07 03 02 01 00 05 04 Sour...

Страница 114: ...R 00H Timer 3 Register T3PDR CC R W 00H Timer 3 PWM Duty Register CDR3 CC R 00H Capture 3 Data Register T3PWHR CD W 00H Timer 3 PWM High Register Table 11 10 Register Map 11 5 2 9 Timer Counter 2 3 R...

Страница 115: ...T2CK 2 0 Select Timer 2 clock source Fx is main system clock frequency T2CK2 T2CK1 T2CK0 Description 0 0 0 fx 2 0 0 1 fx 4 0 1 0 fx 16 0 1 1 fx 64 1 0 0 fx 256 1 0 1 fx 1024 1 1 0 fx 4096 1 1 1 Extern...

Страница 116: ...6 bit 0 8 bit 1 16 bit PWM3E Control PWM enable 0 PWM disable 1 PWM enable CAP3 Control Timer 3 mode 0 Timer Counter mode 1 Capture mode T3CK 1 0 Select clock source of Timer 3 Fx is the frequency of...

Страница 117: ...PD3 T3PD2 T3PD1 T3PD0 R W R W R W R W R W R W R W R W Initial value 00H T3PD 7 0 T3 PWM Duty data NOTE only write when PWM3E 1 CDR3 Capture 3 Data Register Read Case CCH 7 6 5 4 3 2 1 0 CDR37 CDR36 CD...

Страница 118: ...r T4ST T4EN 3 T4CK 2 0 fX INT4 EIEDGE 4 clear INT4IF INT4 Interrupt 16 bit Capture Register T4IF Timer4 Interrupt CDR4H 8 bit CDR4L 8 bit T4DRH 8 bit T4DRL 8 bit 16 bit Timer Data Register comparator...

Страница 119: ...R W R W R W R W R W R W R W Initial value 00H T4EN Control Timer 4 operation 0 Timer 4 disable 1 Timer 4 enable CAP4 Control Timer 4 mode 0 Timer Counter mode 1 Capture mode T4CK 2 0 Select Timer 4 cl...

Страница 120: ...Initial value 00H LCDR4 7 0 T4L Capture data T4H Timer 4 High Register Read Case D5H 7 6 5 4 3 2 1 0 T4H7 T4H6 T4H5 T4H4 T4H3 T4H2 T4H1 T4H0 R R R R R R R R Initial value 00H T4H 7 0 T4H Counter Peri...

Страница 121: ...ear interrupt flag TMIF3 Timer 3 Interrupt Flag 0 No Timer 3 interrupt 1 Timer 3 interrupt occurred write 1 to clear interrupt flag TMIF2 Timer 2 Interrupt Flag 0 No Timer 2 interrupt 1 Timer 2 interr...

Страница 122: ...ZCR 2 1 00 BUZCR 2 1 01 BUZCR 2 1 10 BUZCR 2 1 11 0000_0000 125kHz 62 5kHz 31 25kHz 15 625kHz 0000_0001 62 5kHz 31 25kHz 15 625kHz 7 812kHz 1111_1101 492 126Hz 246 063Hz 123 031Hz 61 515Hz 1111_1110 4...

Страница 123: ...Driver BUZDR Buzzer Data Register 8FH 7 6 5 4 3 2 1 0 BUZDR7 BUZDR6 BUZDR5 BUZDR4 BUZDR3 BUZDR2 BUZDR1 BUZDR0 R W R W R W R W R W R W R W R W Initial value FFH BUZDR 7 0 This bits control the Buzzer...

Страница 124: ...r Empty and RX Complete Double Speed Asynchronous Communication Mode USART has three main parts of Clock Generator Transmitter and Receiver The Clock Generation logic consists of synchronization logic...

Страница 125: ...gister TXSR M U X M U X SS SS Control RXC TXC UMSEL1 UMSEL0 UPM1 UPM0 USIZE2 USIZE1 USIZE0 UCPOL UCTRLx1 ADDRESS E2H FAH INITIAL VALUE 0000_0000B UDRIE TXCIE RXCIE WAKEIE TXE RXE USARTEN U2X UCTRLx2 A...

Страница 126: ...le Speed mode is controlled by the U2X bit in the UCTRLx2 register The MASTER bit in UCTRLx2 register controls whether the clock source is internal Master mode output port or external Slave mode input...

Страница 127: ...is the frequency of main system clock SCLK 11 7 5 Synchronous mode Operation When synchronous or SPI mode is used the XCK pin will be used as either clock input slave or clock output master The depen...

Страница 128: ...an be set to an idle state The idle means high state of data pin The next figure shows the possible combinations of the frame formats Bits inside brackets are optional Figure 11 42 frame format 1 data...

Страница 129: ...ng transmit buffer UDATA register 11 7 8 2 Transmitter flag and interrupt The USART Transmitter has 2 flags which indicate its state One is USART Data Register Empty UDRE and the other is Transmit Com...

Страница 130: ...bit means that a complete serial frame is present in the receiver shift register and contents of the shift register are to be moved into the receive buffer The receive buffer is read by reading the UD...

Страница 131: ...sult with the parity bit from the received serial frame 11 7 9 4 Disabling Receiver In contrast to Transmitter disabling the Receiver by clearing RXE bit makes the Receiver inactive immediately When t...

Страница 132: ...6 for Double Speed mode If more than 2 samples have low levels the received bit is considered to a logic 0 and more than 2 samples have high levels the received bit is considered to a logic 1 The dat...

Страница 133: ...for compatibility to other SPI devices 11 7 10 1 SPI Clock formats and timing To accommodate a wide variety of synchronous serial peripherals from different manufacturers the USART has a clock polarit...

Страница 134: ...out to the MOSI and MISO outputs of the master and slave respectively Unlike the case of UCPHA 1 when UCPHA 0 the slave s SS input must go to its inactive high level between transfers This is because...

Страница 135: ...e of data to the UDATA Register In master mode of operation even if transmission is not enabled TXE 0 writing data to the UDATA register is necessary because the clock XCK is generated from transmitte...

Страница 136: ...served 1 0 1 Reserved 1 1 0 Reserved 1 1 1 9 bit UDORD This bit is in the same bit position with USIZE1 In SPI mode when set to one the MSB of the data byte is transmitted first When set to zero the L...

Страница 137: ...from RXC is inhibited use polling 1 When RXC is set request an interrupt WAKEIE Interrupt enable bit for Asynchronous Wake in STOP mode When device is in stop mode if RXD goes to LOW level an interrup...

Страница 138: ...running while USART is enabled in synchronous master mode 1 XCK is active while any frame is on transferring SPISS Controls the functionality of SS pin in master SPI mode 0 SS pin is normal GPIO or o...

Страница 139: ...here is no data unread in the receive buffer 1 There are more than 1 data in the receive buffer WAKE This flag is set when the RX pin is detected low while the CPU is in stop mode This flag can be use...

Страница 140: ...mode and do not write 0 or 1 in synchronous or SPI mode UDATA USART Data Register E7H FFH 7 6 5 4 3 2 1 0 UDATA7 UDATA6 UDATA5 UDATA4 UDATA3 UDATA2 UDATA1 UDATA0 R W R W R W R W R W R W R W R W Initi...

Страница 141: ...31 0 0 16 2 1 34 0 8 31 0 0 63 0 0 19 2K 11 0 0 23 0 0 12 0 2 25 0 2 23 0 0 47 0 0 28 8K 7 0 0 15 0 0 8 3 5 16 2 1 15 0 0 31 0 0 38 4K 5 0 0 11 0 0 6 7 0 12 0 2 11 0 0 23 0 0 57 6K 3 0 0 7 0 0 3 8 5...

Страница 142: ...transfer or MSB first data transfer 11 8 2 Block Diagram Figure 11 48 SPI Block Diagram 64 32 P r e s c a l e r MUX 2 4 8 16 fSCLK PxDA x SPICR 2 0 3 MUX Edge Detector SPI Control Circuit WCOL TCIR S...

Страница 143: ...use only either transmit or receive clear the TXENA or RXENA In this case user can use disabled pin by GPIO freely 11 8 4 SS pin function 1 When the SPI is configured as a Slave the SS pin is always i...

Страница 144: ...ster SPIDR D3H R W 0H SPI Data Register SPISR D4H R W 0H SPI Status Register Table 11 18 Register Map 11 8 7 SPI Register description The SPI Register consists of SPI Control Register SPICR SPI Status...

Страница 145: ...rial clock SCK mode Clock Polarity CPOL bit determine SCK s value at idle mode Clock Phase CPHA bit determine if data is sampled on the leading or trailing edge of SCK Refer to Figure11 49 Figure 11 5...

Страница 146: ...rupt Requested WCOL This bit is set if the data register SPIDR is written during a data transfer This bit is cleared when user read the status register SPISR and then access read write the data regist...

Страница 147: ...ster operation Up to 400kHz data transfer speed 7 bit address Support two slave addresses Both master and slave operation Bus busy detection 11 9 2 Block Diagram Figure 11 51 I2C Block Diagram SDA F F...

Страница 148: ...d by the master to release the bus lines so that other devices can use it A high to low transition on the SDA line while SCL is high defines a START S condition A low to high transition on the SDA lin...

Страница 149: ...is addressed by a master Address Packet and if it is unable to receive or transmit because it s performing some real time function the data line must be left HIGH by the slave And also when a slave ad...

Страница 150: ...e shortest clock HIGH period A master may start a transfer only if the bus is free Two or more masters may generate a START condition Arbitration takes place on the SDA line while the SCL line is at t...

Страница 151: ...LR to the I2CSDAHR 5 Set the START bit in I2CMR This transmits a START condition And also configure how to handle interrupt and ACK signal When the START bit is set 8 bit data in I2CDR is transmitted...

Страница 152: ...ansfer between master and slave is over To clear I2CSR write arbitrary value to I2CSR After this I2C enters idle state 11 9 8 2 Master Receiver To operate I2C in master receiver follow the recommended...

Страница 153: ...s receiving data from slave To do this set ACKEN bit in I2CMR to ACKnowledge the next data to be received 2 Master wants to terminate data transfer when it receives next data by not generating ACK sig...

Страница 154: ...ion of I2C handling STOP interrupt The STOP bit indicates that data transfer between master and slave is over To clear I2CSR write arbitrary value to I2CSR After this I2C enters idle state 11 9 8 4 Sl...

Страница 155: ...r and slave is over To clear I2CSR write arbitrary value to I2CSR After this I2C enters idle state 11 9 9 Register Map Name Address Dir Default Description I2CMR DAH R W 00H I2C Mode Control Register...

Страница 156: ...eration of I2C 0 Disable interrupt operates in polling mode 1 Enable interrupt ACKEN Controls ACK signal generation at ninth SCL period Note ACK signal is output SDA 0 for the following 3 cases When r...

Страница 157: ...ondition is detected NOTE 0 No STOP condition is detected 1 STOP condition is detected SSEL This bit is set when I2C is addressed by other master NOTE 0 I2C is not selected as slave 1 I2C is addressed...

Страница 158: ...frequency of I2C in master mode fI2C is calculated by the following equation fI2C 1 tSCLK 4 SCLL SCLH 4 I2CSDAHR SDA Hold Time Register DEH 7 6 5 4 3 2 1 0 SDAH7 SDAH6 SDAH5 SDAH4 SDAH3 SDAH2 SDAH1 SD...

Страница 159: ...lows general call address or not when I2C operates in slave mode 0 Ignore general call address 1 Allow general call address I2CSAR1 I2C Slave Address Register 1 D6H 7 6 5 4 3 2 1 0 SLA7 SLA6 SLA5 SLA4...

Страница 160: ...ADCHR and ADCLR contains the results of the A D conversion When the conversion is completed the result is loaded into the ADCHR and ADCLR the A D conversion status bit AFLAG is set to 1 and the A D i...

Страница 161: ...9 ADCO8 ADCO7 ADCO6 ADCO5 ADCO4 ADCO3 ADCO2 ADCO1 ADCO0 ADCRH7 ADCRH6 ADCRH5 ADCRH4 ADCRH3 ADCRH2 ADCRH1 ADCRH0 ADCRL7 ADCRL6 ADCRL5 ADCRL4 ADCRH 7 0 ADCRL 7 4 ADCRL 3 0 bits are 0 Align bit set 1 ADC...

Страница 162: ...n The ADC Register consists of A D Converter Mode Register ADCM A D Converter Result High Register ADCRH A D Converter Result Low Register ADCRL A D Converter Mode 2 Register ADCM2 NOTE 1 when STBY bi...

Страница 163: ...t REFSEL A D Converter reference selection 0 Internal Reference VDD 1 External Reference AVREF AN0 disable AFLAG A D Converter operation state 0 During A D Conversion 1 A D Conversion finished ADSEL 3...

Страница 164: ...TRG TSEL2 TSEL1 TSEL0 ALIGN CKSEL1 CKSEL0 R W R W R W R W R W R W R W R W Initial value 01H EXTRG A D external Trigger 0 External Trigger disable 1 External Trigger enable TSEL 2 0 A D Trigger Source...

Страница 165: ...ACE This enables Analog Comparator When ACE is 0 the output of Comparator goes LOW BGR Band Gap Reference Voltage ACBG This selects input source between BGR and AC When ACBG is 1 the input to AC is BG...

Страница 166: ...Gap Reference Voltage or AN4 0 input is from AN4 1 input is from Band Gap Reference Voltage ACO This bit represents the value of ACOUT Output of Analog Comparator ACO bit is sampled by SCLK system cl...

Страница 167: ...imerP0 4 Operates Continuously Halted Only when the Event Counter Mode is Enable Timer operates Normally Halted Only when the Event Counter Mode is Enable Timer operates Normally ADC Operates Continuo...

Страница 168: ...he device becomes initialized state the registers have reset value Figure 12 1 IDLE Mode Release Timing by External Interrupt Figure 12 2 Figure 1IDLE Mode Release Timing by RESET Ex MOV PCON 0000_000...

Страница 169: ...er is activated on wake up Therefore before STOP instruction user must be set its relevant prescaler divide ratio to have long enough time more than 20msec this guarantees that oscillator has started...

Страница 170: ...start Figure 12 5 Interrupt Enable Flag of All EA of IE should be set to 1 Released by only interrupt which each interrupt enable flag 1 and jump to the relevant interrupt service routine Figure 12 5...

Страница 171: ...r 87H 7 6 5 4 3 2 1 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R W R W R W R W R W R W R W R W Initial value 00H IDLE Mode 01H IDLE mode enable STOP1 2 Mode 03H STOP1 2 mode enable NOTE 1 To enter IDLE...

Страница 172: ...efer Brown Out Detector Enable Table 13 1 Reset state 13 2 Reset Source The MC95FG308 has five types of reset generation procedures The following is the reset sources External RESETB Power ON RESET PO...

Страница 173: ...ise canceller time diagram 13 5 Power on RESET When rising device power the POR Power ON Reset have a function to reset the device If using POR it executes the device RESET function instead of the RES...

Страница 174: ...12ms 250us X 40h about 16ms 00 01 02 03 04 05 06 00 01 02 03 00 01 02 2F 30 F1 3F 40 00 01 02 03 Ext_reset have not an effect on counter value for configure option read Counting for configure option r...

Страница 175: ...nfigure option read Slew Rate 0 025V ms Configure option read point about 1 5V 1 6V Configure option Value is determined by Writing Option Rising section to Reset Release Level 16ms point after POR or...

Страница 176: ...time with 16ms and after the stable state the internal RESET becomes 1 The Reset process step needs 5 oscillator clocks And the program execution starts at the vector address stored at address 0000H...

Страница 177: ...r 4 2V In the STOP mode this will contribute significantly to the total current consumption So to minimize the current consumption the BODEN bit is set to off by software Figure 13 9 Block Diagram of...

Страница 178: ...Register Map 13 7 2 Reset Operation Register Description Reset control Register consists of the BOD Control Register BODR VDD Internal nPOR PAD RESETB R20 BIT for Config BOD_RESETB BIT for Reset INT...

Страница 179: ...reset by writing 0 to this bit or by Power ON reset 0 No detection 1 Detection WDTRF Watch Dog Reset flag bit The bit is reset by writing 0 to this bit or by Power ON reset 0 No detection 1 Detection...

Страница 180: ...he On chip Debug system 14 1 2 Feature Two wire external interface 1 wire serial clock input 1 wire bi directional serial data bus Debugger Access to All Internal Peripheral Units Internal data RAM Pr...

Страница 181: ...and its parity has no error When transmitter has no acknowledge Acknowledge bit is 1 at tenth clock error process is executed in transmitter When acknowledge error is generated host PC makes stop con...

Страница 182: ...14 2 10 bit transmission packet 14 2 2 Packet Transmission Timing 14 2 2 1 Data Transfer Figure 14 3 Data transfer on the twin bus St Sp START STOP DSDA DSCL LSB acknowledgement signal from receiver A...

Страница 183: ...t and stop condition 14 2 2 4 Acknowledge bit Figure 14 6 Acknowledge on the serial bus 1 9 2 10 Data output by transmitter Data output By receiver DSCL from master clock pulse for acknowledgement no...

Страница 184: ...SCL Debugger Serial Clock Line DSDA Debugger Serial Data Line DSDA OUT DSDA I N Host Machine Master Target Device Slave VDD VDD Current source for DSCL to fast 0 to 1 transition in high speed mode pul...

Страница 185: ...or data EEPROM memory Security feature 15 2 Flash and EEPROM Control and status register Registers to control Flash and Data EEPROM are Mode Register FEMR Control Register FECR Status Register FESR Ti...

Страница 186: ...VFY 0 Disable program or program verify mode 1 Enable program or program verify mode ERASE Enable erase or erase verify mode with VFY 0 Disable erase or erase verify mode 1 Enable erase or erase verif...

Страница 187: ...tart to program or erase of Flash and data EEPROM It is cleared automatically after 1 clock 0 No operation 1 Start to program or erase of Flash and data EEPROM READ Start auto verify of Flash or data...

Страница 188: ...ODE Verify mode flag FEARL Flash and EEPROM address low Register F2H 7 6 5 4 3 2 1 0 ARL7 ARL6 ARL5 ARL4 ARL3 ARL2 ARL1 ARL0 W W W W W W W W Initial value 00H ARL 7 0 Flash and EEPROM address low FEAR...

Страница 189: ...W R W R W R W R W R W Initial value 00H TCR 7 0 Flash and EEPROM Time control Program and erase time is controlled by setting FETCR register Program and erase timer uses 10 bit counter It increases b...

Страница 190: ...n by byte or page One page is 32 byte Figure 15 1 Flash Memory Map Figure 15 2 Address configuration of Flash memory 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PAGE ADDRESS WORD ADDRESS Program Memory 0x1F...

Страница 191: ...byte It is mapped to external data memory of 8051 Figure 15 3 Data EEPROM memory map Figure 15 4 Address configuration of data EEPROM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PAGE ADDRESS WORD ADDRESS D...

Страница 192: ...2 1 0 FEMR 4 1 FEMR 5 1 FEMR 2 FECR 6 FECR 7 ERASE VFY PGM VFY OTPE AEE AEF Figure 15 5 The sequence of page program and erase of Flash memory Page Buffer Reset Page Buffer Load 0X00H Erase Erase Lat...

Страница 193: ...Step 4 Read data from Flash 15 4 1 2 Enable program mode Step 1 Enter OCD ISP mode 1 Step 2 Set ENBDM bit of BCR Step 3 Enable debug and Request debug mode Step 4 Enter program erase mode sequence 2 1...

Страница 194: ...8 until all pages are written 15 4 1 4 Flash page erase mode Step 1 Enable program mode Step 2 Reset page buffer FEMR 1000_0001 FECR 0000_0010 Step 3 Select page buffer FEMR 1000_1001 Step 4 Write h0...

Страница 195: ...e mode and select OTP area FEMR 1010_0101 Step 6 Set page address FEARH FEARM FEARL 20 hx_xxxx Step 7 Set FETCR Step 8 Start program FECR 0000_1011 Step 9 Insert one NOP operation Step 10 Read FESR un...

Страница 196: ...ion of Data EEPROM are executed by direct and indirect address mode Direct address mode uses external data area of 8051 Indirect address mode uses address register of SFR area 15 4 2 1 Data EEPROM Rea...

Страница 197: ...00_0001 FECR 0000_0010 Step 3 Select page buffer FEMR 0100_1001 Step 4 Write h00 to page buffer Data value is not important Step 5 Set erase mode FEMR 0101_0001 Step 6 Set page address FEARH FEARM FEA...

Страница 198: ...read Read cell by byte Flash write Write cell by bytes or page Flash page erase Erase cell by page Flash bulk erase Erase the whole cells Flash program verify Read cell in verify mode after programmin...

Страница 199: ...nificant byte selects memory to be accessed Table 15 4 shows memory type to be accessible by parallel mode Address auto increment is supported when read or write data without address The erase and pro...

Страница 200: ...th 2 byte address nALE L L H H H H H nWR L H L H H H H H H H H H H H nRD H H H H L H L H L H L H L H PDATA ADDRL ADDRM DATA0 DATA1 DATA2 DATAn n byte data write with 2 byte address nALE L L H H H H H...

Страница 201: ...AL AM AH Data AL AM Data AL Data Out Data 1 byte write with 3 byte address 1 byte write with 2 byte address 2 byte write with 1 byte address Write 0x03 0x0A002 DI 00H DI 01H DI 02H DI 03H T WH nALE TD...

Страница 202: ...mode 15 6 2 Mode entrance of Byte parallel TARGET MODE P0 3 0 P0 3 0 P0 3 0 Byte Parallel Mode 4 h5 4 hA 4 h5 Figure 15 11 Byte parallel mode Power on reset nTEST DSDA R0 3 0 RESET_SYSB h5 hA h5 Rele...

Страница 203: ...LOCK E LOCK F R W P E B E R W P E B E R W P E B E R W P E B E R W P E B E R W P E B E 0 0 O O O X O O O O X X X X O O O O O O O O O O O O 0 1 O O O X O O O O X X X X X X X O O O O O O X X O 1 0 O O O...

Страница 204: ...s applied 00 0100H 01FFH default 01 0100H 03FFH 10 0100H 07FFH 11 0100H 0FFFH SXINEN Enable External Sub Oscillator 0 Sub OSC disable default 1 Sub OSC Enable XINENA Enable External Main Oscillator 0...

Страница 205: ...irect byte to A with carry 2 1 35 ADDC A Ri Add indirect memory to A with carry 1 1 36 37 ADDC A data Add immediate to A with carry 2 1 34 SUBB A Rn Subtract register from A with borrow 1 1 98 9F SUBB...

Страница 206: ...o A 1 1 46 47 ORL A data OR immediate to A 2 1 44 ORL dir A OR A to direct byte 2 1 42 ORL dir data OR immediate to direct byte 3 2 43 XRL A Rn Exclusive OR register to A 1 1 68 6F XRL A dir Exclusive...

Страница 207: ...C A A DPTR Move code byte relative DPTR to A 1 2 93 MOVC A A PC Move code byte relative PC to A 1 2 83 MOVX A Ri Move external data A8 to A 1 2 E2 E3 MOVX A DPTR Move external data A16 to A 1 2 E0 MOV...

Страница 208: ...el Compare register immediate jne relative 3 2 B8 BF CJNE Ri d rel Compare indirect immediate jne relative 3 2 B6 B7 DJNZ Rn rel Decrement register jnz relative 2 2 D8 DF DJNZ dir rel Decrement direct...

Страница 209: ...any error by using compare jump instructions If input signal is fixed there is no error in using compare jump instructions Error status example Preventative measures 2 cases Do not use input bit port...

Страница 210: ...to copy the input port as internal parameter or carry bit and then use compare jump instruction zzz MOV C 080 0 input port use internal parameter MOV 020 0 C move JB 020 0 xxx compare SETB 088 0 SJMP...

Страница 211: ...Out Detector Characteristics 30 7 8 Internal RC Oscillator Characteristics 31 7 9 Ring Oscillator Characteristics 31 7 10 PLL Characteristics 31 7 11 DC Characteristics 32 7 12 AC Characteristics 33...

Страница 212: ...egister Map 59 10 13 Interrupt Register Description 59 10 13 1 Register Description for Interrupt 60 11 Peripheral Hardware 66 11 1 Clock Generator 66 11 1 1 Overview 66 11 1 2 Block Diagram 66 11 1 3...

Страница 213: ...ock Diagram 122 11 6 3 Register Map 123 11 6 4 Buzzer Driver Register Description 123 11 6 5 Register Description for Buzzer Driver 123 11 7 USART 124 11 7 1 Overview 124 11 7 2 Block Diagram 125 11 7...

Страница 214: ...ap 166 11 11 5 Analog Comparator Register Description 166 11 11 6 Register Description for USI0 166 12 Power Down Operation 167 12 1 Overview 167 12 2 Peripheral Operation in IDLE STOP Mode 167 12 3 I...

Страница 215: ...mode 195 15 4 1 9 Flash program verify mode 195 15 4 1 10 OTP program verify mode 196 15 4 1 11 Flash erase verify mode 196 15 4 1 12 Flash page buffer read 196 15 4 2 Data EEPROM operation 196 15 4...

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