BIOS Setup
IP35V
2-11
2.4 Advanced Chipset Features
Phoenix – AwardBIOS CMOS Setup Utility
Advanced Chipset Features
DRAM Timing Selectable
By SPD
Item Help
x - CAS Latency Time
(tCL)
Auto
x - RAS# to CAS# Dealay (tRCD) Auto
x - RAS# Precharge
(tRP)
Auto
x - Precharge Delay
(tRAS) Auto
x - Refresh Cycle Time
(tRFC) Auto
x - Write Recovery Time (tWR)
Auto
x - Write to Read Delay (tWTR) Auto
x - Act to Act Time
(tRRD) Auto
x - Read to Precharge
(tRTP) Auto
x - Command Rate
Auto
►
PCIe Root Port Function
Press Enter
Init Display First
PCI Slot
PEG Force X1
Disabled
:Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults
DRAM Timing Selectable
This item sets the optimal timings for the following four items, depending on the memory
module you are using. The default setting “By SPD” configures these four items by reading the
contents in the SPD (Serial Presence Detect) device. The EEPROM on the memory module
stores critical parameter information about the module, such as memory type, size, speed,
voltage interface, and module banks. The following items will be available to make adjustments
by selecting option [
Manual]
.
-
CAS Latency Time
(tCL)
-
RAS# to CAS# Dealay (tRCD)
- RAS#
Precharge
(tRP)
- Precharge
Delay
(tRAS)
-
Refresh Cycle Time
(tRFC)
-
Write Recovery Time (tWR)
-
Write to Read Delay
(tWTR)
-
Act to Act Time
(tRRD)
-
Read to Precharge
(tRTP)
- Command
Rate
Содержание IP35V
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