abaco systems XVR16 Series, Справочник по аппаратуре, Страница: 83 / 151

Publication No. 500-9300007876-000 Rev. C.0 FPGA Registers 83
8.1 FPGA Control and Status Registers
The XVR16 FPGA contains an LPC interface for access to real-time user functions
such as Watchdog timer, 32-bit Timers, and GPIO. There are also control and
status registers for other board functions such as BIT, Board/Front Panel Options,
NVRAM Page control, and COM Port Configuration. The FPGA registers are
mapped in I/O space staring at address 0x600.
See Table 8-1 for the list of XVR16 FPGA Registers.
Table 8-1 XVR16 FPGA Register Definitions
LPC I/O Port (Hex) Description Access
600 Board ID Read
601 Board Revision Read
602-060A Reserved NA
60B FPGA Revision Read
60C Reserved NA
60D Watchdog Timers (WDT) Refresh Read/Write
60E Watchdog Timer CSR (LSB) Read/Write
60F Watchdog Timer CSR (MSB) Read/Write
610 to 61A Board ID String Read
61B Reset Cause Register 1 Read
61C Reset Cause Register 2 Read
61D-61F Reserved NA
620 BMM/BMC Control Read/Write
621 Reserved NA
622 LED Control Read/Write
623 Reserved NA
624 Reserved NA
625 BIOS/SPI Control Read/Write
626-628 Reserved NA
629 BIT Control/Status Register Read/Write
62A-62D Reserved NA
62E-631 Reserved NA
632-634 Reserved NA
635 NVRAM Memory Space Page Register Read/write
636-647 Reserved NA
648-64F Reserved NA
650 Timer 0 CSR1 Read/Write
651 Timer 0 CSR2 Read/Write
652 Timer 0 IRQ Clear Write to Clear
653 Reserved NA
654 Timer 0 Byte 0 (LSB) Read/Write
655 Timer 0 Byte 1 Read/Write
656 Timer 0 Byte 2 Read/Write
657 Timer 0 Byte 3 (MSB) Read/Write