Publication No. 500-9300527837-000 Rev. A.0
Functional Description 51
5.16 Timers
5.16.1 General Purpose Timers
The timer/counter block within the PCH contains three counters that are
equivalent in function to those found in one 82C54 programmable interval timer.
These three counters are combined to provide the system timer function and
speaker tone. The 14.31818 MHz clock (derived internally within the PCH)
provides the clock source for these three counters.
The FPGA provides two additional 32-bit counters. The source clock for these
counters is 2 MHz, and a programmable pre-scaler can be used to achieve 1:2, 1:4,
or 1:8 reduction of the 2 MHz clock input. The timers can be programmed to
generate an SERIRQ interrupt on expiry, and any 32-bit value can be loaded into
the timer as a start value. The timers can be programmed to roll-over on expiry
and reload the initial start value, or they can be programmed into one-shot mode
where they will stop counting when expired. Together, these features provide a
highly flexible timer solution.
The FPGA timers are intended only to be used by Abaco software drivers. See the
relevant software manual for details.
5.16.2 Watchdog Timer
The FPGA provides one Watchdog timer, capable of resetting the SBC347A on
expiry. This has a timeout interval selectable from the following:
• 2 milliseconds
• 32 milliseconds
• 131 milliseconds
• 262 milliseconds
• 524 milliseconds
• 2.1 seconds
• 33 seconds
• 66 seconds
Following reset, the Watchdog is initially disabled. It can be enabled and the
timeout period selected by software through the FPGA. Once enabled, the
Watchdog must be serviced periodically. If the timeout expires before the
Watchdog is serviced, then a hard reset is generated. Software can also disable the
Watchdog through the FPGA.
