abaco systems PPC11A, Справочник по аппаратуре

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Publication No. PPC11A-HRM/1 Functional Description 53
4.19.2 PCIe Switches
The PPC11A has two PEX8619 16-lane PCIe switches, which connect the processor to
PCIe devices as shown in Figures
4-2 and 4-3 . The default switch port configurations
are shown below.
Table 4-24 PCIe Switch 1 Connections
Port Lane(s) Width Link To Speed Lane Reversal Direction
0 0 to 3 x4 Processor Gen2 No Up
1 8 to 11 x4 XMC site 1/
PMC site 1
Gen2/
Gen1
N/A Down
2 4
7
x1
x1
Ethernet 1
Ethernet 2
Gen1 No Down
3 12 x1 UART Gen1 N/A Down
11 13 x1 1553 Gen1 No Down
13 14 x1 SATA Gen1 No Down
15 15 x1 VME Bridge Gen1 No Down
Table 4-25 PCIe Switch 1 Connections
Port Lane(s) Width Link To Speed Lane Reversal Direction
0 0 to 3 x4 Processor Gen2 No Up
1 8 to 11 x4 XMC site 2/
PMC site 2
Gen2/
Gen1
N/A Down
2 4
7
x1
x1
Ethernet 3
Ethernet 4
Gen1 No Down
3 Not used
11 Not used
13 14 x1 Not used No Down
15 15 x1 Not used No Down
The switches are connected to I
2
C Bus 3 to allow configuration by the processor and
out-of-band link status monitoring.
Each PCIe port of the switch appears to software as a PCI-to-PCI bridge, with its
own PCI- compatible configuration registers. Each port is accessed on the internal
virtual PCI bus using a device number equal to its port number.
Port 0 also contains a DMA function, containing two DMA channels, for transferring
data between a PCIe device and processor RAM or another PCIe device, with
minimal overhead on the host processor.
The switch also supports multicast addressing, as defined by PCIe Base Specification
2.1, allowing PCIe writes to be forwarded to multiple destinations.
The port configuration of the switch is initially set up by hardware strapping. Each
port can negotiate down to smaller link widths if required (such as if a fault occurs
on a lane). Port widths of x1, x2, and x4 are supported.