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SBC-554V/555 User's Manual
R O M P C I / I S A B I O S ( 2 A 5 I I A K 9 )
C M O S S E T U P U T I L I T Y
C H I P S E T F E A T U R E S S E T U P
Esc:Quit
áâàß
: Select Item
F1 : Help
PU/PD/+/- : Modify
F5 : Old Values
(Shift)F2 : Color
F6 : Load BIOS Defaults
F7 : Load Setup Defaults
Auto Configuration
: Enabled
L2(WB) Tag Bit length
: 8 bits
SRAM Back-to-Back
: Enabled
NA# Enable
: Disabled
Starting point of paging
: 1T
Refresh Cycle Time (US)
:
187.2
RAS Pulse Width Refresh
: 6T
RAS precharge Time
: 4T
RAS to CAS Delay
: 4T
CAS# Pulse Width (FP)
: 2T
CAS# Pulse Width (ED0)
: 1T
RAMW# Assertion Timing
: 3T
CAS Precharge Time (FP)
: 1T/2T
CAS Precharge Time (EDO) : 1T/2T
Read Prefetch Memory RD
: Enabled
CPU to PCI Post Write
: 3T
CPU to PCI Burse Mem. WR : Disabled
ISA Bus Clock Frequency
: PCI CLK/4
System BIOS Cacheable
: Enabled
Video BIOS Cacheable
: Enabled
Memory Hole at 15M-16M
: Disabled
CHIPSET features setup
By choosing the CHIPSET FEATURES SETUP option from the
INITIAL SETUP SCREEN menu, the screen below is displayed.
The following configurations are based on the manufacturers
SETUP DEFAULTS settings.
This section allows you to configure the system based on the
specific features of the installed chipset. This chipset manages bus
speeds and access to system memory resources, such as DRAM
and the external cache. It also coordinates communications
between the conventional ISA bus and the PCI bus. It must be
stated that these items should never need to be altered. The default
settings have been chosen because they provide the best operating
conditions for your system.
The only time you might consider making any changes would be
if you discovered that data was being lost while using your system.
Содержание SBC-555
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