Chapter 3 Award BIOS Setup
55
PCI Delay Transaction
The chipset has an embedded 32 -bit posted write buffer to support
delay transactions cycles. Select enabled to support compliance
with PCI specification version 2.1.
The choices: Enabled, Disabled.
PCI#2 Access #1 Retry
When disabled, PCI#2 will be connected until access
finishes(default). When enabled, PCI#2 will be disconnected if max
retries are attempted without success.
The choices: Enabled, Disabled.
AGP Master 1 WS Write
System will run
single wait state delay
before writing data from
buffer. If the setting is configured as disabled, system will run
twice
wait states
so that system can be more stable.
The choices: Enabled, Disabled.
AGP Master 1 WS Read
System will run
single wait state delay
before reading data from
buffer. If the setting is configured as disabled, system will
run twice
wait states
so that system can be more stable.
The choices: Enabled, Disabled.
Содержание PCM-6892 Rev.B
Страница 18: ...8 PCM 6892 Installation GuideBC PCM 6892 Locating Jumpers Connectors ...
Страница 19: ...PCM 6892 Installation Guide 9 Quick Installation Guide Locating Jumpers Connectors ...
Страница 20: ...10 PCM 6892 Installation GuideBC PCM 6892 Mechanical Drawing ...
Страница 21: ...PCM 6892 Installation Guide 11 Quick Installation Guide Mechanical Drawing ...
Страница 98: ...Appendix A Watchdog Timer 91 A WatchDog Timer A P P E N D I X ...
Страница 105: ...Appendix B Optional Extras 99 B Optional Extras A P P E N D I X Appendix B pmd 2003 10 21 09 21 上午 99 ...