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Page 1: ...utilized and idle equipment along with credit for buybacks and trade ins Custom engineering so your equipment works exactly as you specify Critical and expedited services Leasing Rentals Demos In stoc...

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Page 8: ...3 XVME 500 3 and XVME 590 3 programmable gain amp with 10uSec conversion See Table l l Section 1 3 for additional information on conversion time settling time and throughput frequency for each version...

Page 9: ...escriptions block diagram assembly illustration and schematics and a quick reference section 1 3 MODULE OPERATIONAL DESCRIPTION Figure l 1 shows the operational block diagram of the XVME 500 and Figur...

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Page 12: ...the ADC expansion kit allows double signal input directed by software to select one channel for data conversion Resistor programmable gain with addition of a resistor and a potentiometer 1 3 2 Genera...

Page 13: ...l Range 1 xl x2 x5 and x10 Range 2 x4 x8 x20 and x40 Range 3 x10 x20 x50 and x100 A 32 element RAM buffer is provided with the programmable amps to hold separate gain values for the 32 analog inputs W...

Page 14: ...rity Differential Linearity Monotonicity 12 bits 0 5 LSB 50 5 LSB Guaranteed System Accuracy Gain 1 Gain 10 Gain 100 0 0l FSR max 0 l FSR max 01 FSR max System Accuracy Temperature Drift Gain 1 40 ppm...

Page 15: ...ode Voltage Speed Conversion Time versions 1 2 version 3 Throughput Frequency version 1 version 2 version 3 Settling Time version 1 versions 2 3 1 2 5 or 10 4 8 20 or 40 10 20 50 or 100 xl x10 x100 xl...

Page 16: ...ating 50g peak acceleration 11 mSec duration Vibration Operating 5 to 2000Hz 015 in peak to peak 2 5g max Non operating 5 to 2OOOHz 030 in peak to peak 5 Og max VMEbus Compliance 0 Complies with VMEbu...

Page 17: ...0 All bit definitions for registers are the same EXCEPT there are no LEDs Channel register counter now reset the 540 powers up random receives reset software power up l No fast convert in single chan...

Page 18: ...ne A properly installed controller subsystem An example of such a subsystem is the XYCOM XVME 010 System Resource Module B A host processor which incorporates an on board controller subsystem such as...

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Page 23: ...2 5 3 Module base address select jumpers Section 2 5 1 refer to This jumper allows module to respond to supervisory access only when installed or to both supervisory and non privileged access when re...

Page 24: ...ection 3 4 1 These two jumpers are provided to allow grounding of an input channel in either the single ended or the differential input mode of operation for purposes of calibration see Section 2 6 5...

Page 25: ...A l 4 A l 3 A l 2 A l l co A10 l Figure 2 3 Base Address Jumpers When a jumper is INSTALLED the corresponding base address bit will be logic 0 However when a jumper is REMOVED the corresponding base a...

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Page 27: ...nterrupt at the completion of a conversion These jumpers determine the level of that interrupt Interrupt level jumper options are defined in Table 2 4 In order to enable interrupts a bit in the Status...

Page 28: ...ge modes Table 2 5 Input Conversion Format Jumpers Digital Data Conversion Jumpers Input Format All Inputs Installed Mode Analog to Straight Binary JlA J4A Analog to Offset Binary JlA J4A Analog to Tw...

Page 29: ...reases to 16 Table 2 6 Single Ended Differential Pseudo Differential Jumper Options Jumpers Set J21A J21C J25 Input Mode Set in this manner the module inputs are configured for single ended opera tion...

Page 30: ...XVME 500 590 2 XVME 500 590 3 J15 J19 J14 J18 J16 J20 The gain for each input channel is individually programmable over any one of three possible gain ranges First the required range is selected by c...

Page 31: ...table version 1 only J6 J7 J8 or J9 The fixed gain for each analog input channel in the version 1 of the XVME 500 590 is selected by installing or removing one of several jumpers J6 J7 J8 or J9 Gains...

Page 32: ...l In order to utilize these gains it is necessary to install 1 A fixed value resistor value determined by equation following 2 A potentiometer for fine adjustment of the gain and 3 A cut on the printe...

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Page 35: ...K 614 to achieve the desired value NOTE The resistor used should be type RN 55E with a temperature coefficient of 25 ppm Degree C max 6 The resistor RI0 should be soldered in the position designated b...

Page 36: ...solution jumpers Table 2 10 Conversion Resolution Jumpers I Conversion Desired Jumper Installed I 1 12 bit J2A 8 bit J2B Figure 2 5 shows the various formats of the data input register when either J2A...

Page 37: ...nel 8 to ground Inserting J24 shorts channel 0 to ground In differential mode inserting both J23 channel 0 Hi and J24 channel 0 Lo will short channel 0 to ground Table 2 11 shows the relationship betw...

Page 38: ...H 26 ANALOG GND CH 27 CH 19 ANALOG GND CH 20 CH 28 Those channels marked by are only available expansion kit is installed Table continued next page Differential Configuration CH 0 LO CH 0 HI ANALOG GN...

Page 39: ...onnections for Pl a 96 pin 3 row connector contains the standard address data and control signals necessary for the operation of VMEbus defined NEXP modules The signal definitions and pin outs for the...

Page 40: ...1 ANALOG GND CH 22 CH 30 ANALOG GND Differential Configuration P2 Connector CH 0 LO Cl CH 0 HI Al ANALOG GND C 2 CH 1 HI A2 CH 1 LO C 3 ANALOG GND A3 CH 2 LO C 4 CH 2 HI A4 ANALOG GND c 5 CH 3 HI A5 C...

Page 41: ...o s complement conversion with J1B Unipolar voltage range selector Bipolar voltage range selector Fixed gain selector x1000 Resistor programmable gain selector Fixed gain selector x100 Fixed gain sele...

Page 42: ...s select jumper Module base address select jumper Module base address select jumper Module base address select jumper Module base address select jumper XVME 590 Only J32 is jumpered in foil to connect...

Page 43: ...ations and all connections to external devices or power supplies Please check the jumper configuration against the diagrams and lists in this manual To install a board in the cardcage perform the foll...

Page 44: ...he module from the bus 3 Remove the screw and plastic collar assemblies labeled 6 7 from the extreme top and bottom of the existing 3U front panel 11 4 Install the screw assemblies in their correspond...

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Page 46: ...n a system it will occupy a IK byte block of the Short I O Address Space The base address decoding scheme for the XVME I O modules positions the starting address for each board on a 1K boundary Thus t...

Page 47: ...E D w w m s w Status Control Reg Interrupter Vector Reg w i Gain Channel Reg A D High Byte A D Low Byte U N D E F I N E D 7FH 81H 83H 85H 87H rlgure 3 l XVME 500 590 Analog Input Module Memory Map 3 2...

Page 48: ...ster base 81H Section 3 3 1 The status control register contains eight single bit locations which provide control signals to reset the module enable interrupts start conversion show if there are inter...

Page 49: ...r 3 3 1 1 Bit No Function I Status Control 0 1 2 Interrupt Pending No Connection 3 Interrupt Enable Interrupt Enable 4 Board Reset Board Reset 5 Mode 0 Mode 0 6 Mode 1 Mode 1 7 A D Busy Convert Status...

Page 50: ...of input conversion modes is explained in greater detail in Section 3 4 1 D4 This bit provides a means for a module software reset If toggled to logic l then back to logic 0 a software reset will occu...

Page 51: ...2 and 2 6 4 3 realizes gains in one of two non software methods The first method is gain selection via jumpers This method allows the input channels to be programmed for a specific gain in one range...

Page 52: ...3 I XVME 500 l D7 D6 05 04 03 02 Dl D O Selects Gain 00 Gain 1 01 Gain 2 10 Gain 3 11 Gain 4 I Selects Channel I Configures the Register to Program Iogic 1 or to Read Convert the gain Figure 3 2 Gain...

Page 53: ...2 1 Channel 3 0 Channel 4 1 Channel 5 0 Channel 6 1 Channel 7 0 Channel 8 1 Channel 9 0 Channel 10 1 Channel 1I 0 Channel 12 1 Channel 13 0 Channel 14 1 Channel 15 0 Channel 16 1 Channel 17 0 Channel...

Page 54: ...in RAM or it allows the register to be used to read the gain RAM The specific channel can be programmed to apply the chosen gain factor any time it converts a signal as follows 1 Write logic 1 to bit...

Page 55: ...ee Figure 3 4 07 06 05 04 03 02 01 DO X X 0 0 1 1 1 1 1 I Gain Factor Enables Selects Channel is read here Register for 15 for a gain Convert Mode Read Convert Figure 3 4 Conversion at Channel 15 3 3...

Page 56: ...D5 D4 D3 D2 Dl D O Base 86H Base 87H Figure 3 5 A D Data Input Register Format The manner in which data appears at the A D Data Register depends upon which input operation mode has been previously pro...

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Page 59: ...terrupt level input type DI or SE and bipolar or unipolar input voltage range input gain range and input binary data format straight binary offset binary or two s complement Initialization see Section...

Page 60: ...nnector JKI Four conditions may cause a conversion to be initiated These conditions are 1 Writing to the channel gain register in random channel mode with data bit 5 at a logic 0 2 Reading the low byt...

Page 61: ...0 Select the desired channel by writing the channel number to bits D0 thru D4 of the gain channel register base 85H Assuming the cor responding Gain RAM was properly initialized programmed after powe...

Page 62: ...n will force a conversion on the specified starting channel without incrementing the channel number Then by reading the low order A D data byte base 87H the channel number will be incremented by one a...

Page 63: ...with the correct gain on a specified channel A conversion may also be forced by using bit D7 of the status control register 3 The result of the conversion can be read from the A D data registers base...

Page 64: ...number to bits D0 thru D4 of the gain channel register Assuming that the Gain RAM was properly initialized programmed after power up it will not be necessary to rewrite the gain at this time unless a...

Page 65: ...ection 2 5 3 2 The Interrupt Vector Register location base 83H must be loaded with the required vector This vector register will be read by the interrupt handler when the interrupt is acknowledged 3 I...

Page 66: ...l tolerance or better with stable temperature coefficient characteristics e g 25ppm or better All input channels operate with the same full scale input range 3 21 Artisan Scientific Quality Instrumen...

Page 67: ...bration Potentiometers Resistor R2 R8 R9 R17 Rll R13 Description ADC unipolar offset adjust ADC bipolar offset adjust ADC gain adjust Input offset adjust Prog Gain version 2 and 3 only Input Offset fo...

Page 68: ...n to 10 by setting bits D6 and D7 of the Gain Channel register to logic 1 Measure and record the output voltage V at TP2 6 Calculate the voltage offset with the following formula Voltage Offset Voos 1...

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Page 72: ...input analog multi plexers Installation is simply a matter of positioning the two integrated circuits on the board in locations U19 and U23 and soldering them in place see Appendix C the assembly draw...

Page 73: ...nal Name and Description AC FAILURE Open collectors driven signal which indicates that the AC input to the power supply is no longer being provided or that the required input voltage levels are not be...

Page 74: ...ole driven signal generated by the bus arbitrator to request release by the DTB master if a higher level is requesting the bus BUS ERROR Open collector driven signal generated by a slave It indicates...

Page 75: ...ord transfers that a data transfer will occur on data buss lines D00 D07 DATA STROBE 1 Three state driven signal that indicates during byte and word transfers that a data transfer will occur on data b...

Page 76: ...signals generated by an interrupter which carry prioritized interrupt requests Level seven is the highest priority LONGWORD Three state driven signal indicates that the current transfer is a 32 bit tr...

Page 77: ...e system to be reset WRITE lA 14 WRITE Three state driven signal that specifies the data transfer cycle in progress to be either read or written A high level indicates a read operation a low level ind...

Page 78: ...BSY DO1 BCLR DO2 ACFAIL DO3 BG0IN DO4 BGOOUT DO5 BGlIN DO6 BGlOUT DO7 BG2IN GND BG20UT SYSCLK BG3IN GND BG30UT DSl BRO DSO BRl WRITE BR2 GND BR3 DTACK AM0 GND AM1 AS AM2 GND AM3 IACK GND IACKIN IACKOU...

Page 79: ...A 14 PA20I NO CONNECT P2C 14 PA3 1 P2A 15 PA1 1 NO CONNECT P2C 15 GND P2A 16 GND NO CONNECT P2C 16 PAO 1 P2A 17 H4 OUT 2 NO CONNECT P2C 17 G N D P2A 18 TMR OUT 2 NO CONNECT P2C 18 H2 OUT 2 P2A 19 H2 I...

Page 80: ...rs provide the option of converting analog inputs to either a two s complement straight binary or offset binary format See Section 2 6 1 Selects 12 bit conversions for analog to digital converter See...

Page 81: ...pseudo differential input channels Section 2 6 2 J22A J22B J22C J22D J23 J24 Each jumper is used to determine settling times for the appropriate module amplifier Section 3 4 1 These two jumpers are p...

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Page 83: ...HI 17 CH 5 CH 5 LO 18 ANALOG GND ANALOG GND 19 CH 6 CH 6 LO 20 CH 14 CH 6 HI 21 ANALOG GND ANALOG GND 22 CH 15 CH 7 HI 23 CH 7 CH 7 LO 24 ANALOG GND ANALOG GND 25 CH 16 CH 8 LO 26 CH 24 CH 8 HI 27 ANA...

Page 84: ...42 ANALOG GND ANALOG GND 43 CH 22 CH 14 LO 44 CH 30 CH 14 HI 45 ANALOG GND ANALOG GND 46 CH 31 CH 15 HI 47 CH 23 CH 15 LO 48 ANALOG GND ANALOG GND 49 POWER GND PD GND POWER GND PD GND 50 EXT TRIGGER E...

Page 85: ...NALOG GND CH 22 CH 30 ANALOG GND Differential Configuration P2 Connector CH 0 LO Cl CH 0 HI Al ANALOG GND C 2 CH 1 HI A2 CH 1 LO C 3 ANALOG GND A3 CH 2 LO C 4 CH 2 HI A4 ANALOG GND C5 CH 3 HI A5 CH 3...

Page 86: ...or programmable gain selector Fixed gain selector x100 Fixed gain selector x10 A3 interrupt level selector A2 interrupt level selector Al interrupt level selector IN supervisory only OUT supervisory o...

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Page 88: ...2 XVME 500 590 Analog Input Module Memory Map Table C 6 A D Calibration Potentiometers Resistor R2 R8 R9 R17 Rll R13 Description ADC unipolar offset adjust ADC bipolar offset adjust ADC gain adjust In...

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Page 104: ...uipment Have surplus equipment taking up shelf space We ll give it a new home Learn more Visit us at artisantg com for more info on price quotes drivers technical specifications manuals and documentat...

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