Xerox CX PRINT SERVER 550 Reference Manual Download

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Summary of Contents for CX PRINT SERVER 550

Page 1: ...Xerox 550 Computer Reference Manual 90 30 77A...

Page 2: ...Xerox Corporation 701 South Aviation Boulevard EI Segundo California 90245 213 679 4511 Xerox 550 Computer Reference Manual FIRST EDITION 90 30 77A February 1974 Price 6 50 XEROX Printed In S A...

Page 3: ...nce Manual 90 1790 Xerox Meta Symbol LN OPS Reference Manual 900952 Xerox Macro Symbol LN OPS Reference Manual 90 1578 Manual Content Codes BP batch processing LN language OPS operations RP remote pro...

Page 4: ...er 13 XW 54 Main Memory 14 STB 54 Memory Unit 14 STH 55 Maintainability and Performance 16 STW 55 Virtual and Real Memory 17 STD 55 Types of Addressing 19 STS 55 Memory Address Control 26 STM 55 Progr...

Page 5: ...emory Map 98 LMAP 98 LMAPRE 98 Loading the Access Protection Controls 98 Memory Write Protection Locks 99 LLOCKS 99 LLOCKSE 99 Interruption of MMC 100 Memory Access Traps by MMC Instruction __ 100 LRA...

Page 6: ...s 13 ZCMM6 143 ZCMM7 144 4 Main Memory 15 ZCMM8 144 ZCMM9 144 5 Addressing Logic 18 L MMA i44 ZCLDS 144 6 Index Displacement AI ignment Real and ZCLDT 144 Virtua I Addressing Modes 21 ZCT 144 System C...

Page 7: ...36 6 ANALYZE Table for Operation Codes 56 22 Diagnostic Control P Mode Commands 140 7 Floating Point Number Representation 75 23 Bit Assignments and Description Processor 8 Condition Code Settings for...

Page 8: ...ration Parity checking is performed on each byte of information for most system interfaces and internal control signals Most failed instructions are automatically retried and uninter rupted processing...

Page 9: ...irection on buses be tween memory units and processors providing fault 2 General Characteristics detection and location capability to permit the operati ng system or diagnostic program to quickly dete...

Page 10: ...r via common carrier lines and local terminals directly STANDARD AND OPTIONAL FEATURES A basic system has the following standard features A basic processor BP that includes Full instruction set Memory...

Page 11: ...its intervention 4 Time Shari ng Features Interpret Instruction The Interpret instruction simplifies and speeds interpretive operations such as compilation thus reducing space and time requirements fo...

Page 12: ...set of the total system may be logically isolated partitioned so that maintenance may proceed on the subset whi Ie the remainder of the system conti nues to operate To minimize the effect of transient...

Page 13: ...ltiple capa bi Iity makes the system particularly effective in multi use applications The major multiuse features are described in the follow ing paragraphs 6 Muitiuse Features Multiprocessor Features...

Page 14: ...stems This function provides these basic features 1 Control of the External Direct Input Output bus Ex ternal 010 used for controlling system maintenance and special purpose units such as analog to di...

Page 15: ...ipheral devices The MIOP com municates with device controllers via the I o bus which connects to the Controller Interface CI SYSTEM CONTROL PROCESSOR The System Control Processor performs these primar...

Page 16: ...I I I rocessoq BUS 1fT T I I J r L System Control I Processor I L_ _J r I System I I Control I LC o J Externa I Interrupts 0 T I r II I 1 11 _ _ DIO Bus Communications 1 Interface Line Adapter Line Ad...

Page 17: ...rocessor Index Registers oIndirect Access Flag o III II II I Operation Code Field 1 7 J General Register Designator 8 11 ITO Index Register Designator 12 14 Reference Address Field IIII111111111111111...

Page 18: ...be broken into 512 word pages and dy namically relocated throughout memory in whatever pages of space are avai lable When the memory map is not in effect all virtual address values above 1510 are used...

Page 19: ...es tablished by the resident operating system MAPPED MODE Although the memory map is located in the Memory Inter face MI it functions as part of the basic processor The basic processor communicates w...

Page 20: ...n mem ory may have the following format Bits o 1 7 8 11 Description Indirect addressing One level of indirect ad dressing is performed only if this bit position con tains a one Operation code This 7 b...

Page 21: ...its may con tain two four or six ports which have a fixed priority order for the resolution of contention problems The following sections describe the organization and opera tion of the memory system...

Page 22: ...mory Unit Driver MD P P P P P P 1 2 3 4 5 6 Memory Bus 1 1 Memory Bus 2 Processor Cluster To Processor Bus es Maximum of eight Core Core Memory Memory Modules Modules CMM CMM Memory Memory Memory Unit...

Page 23: ...essor i e basic processor or MIOP can gain 16 Main Memory access to a given memory location without encountering interference from another processor that is making sequen tia I requests Two memory uni...

Page 24: ...nt sections See also Figure 5 wh ich illustrates the control and data flow during address generation 1 Instruction Address This is the address of the next instruction to be executed For real real exte...

Page 25: ...write protect violation 0 END Figure 5 Addressing Logic 18 Main Memory Fetch contents of register Add 20 22 bit index to 17 bit direct reference address or 20 bit indirect reference address 20 22 bit...

Page 26: ...ress is defined as the final virtual address computed for an instruction Note however that some instructions do not use the effective address as a location reference instead the effective address is u...

Page 27: ...tion register that initially contains zeros in the two low order bit positions 32 and 33 The displacement value from the index register is then aligned with the instruction register as an integer acco...

Page 28: ...or incrementing at the halfword address level The final effective virtual address is formed by the address gen erator and if the value of the reference address is greater than 15 the effective virtual...

Page 29: ...ct address Halfword operation indexing alignment Effective virtual address The 8 high order bits of the effective address are replaced with ll bit page address N from memory map Final memory address w...

Page 30: ...any carry resulting from the addition Instruction in memory information used by address generator Byte operation indexing alignment Indexed not indexed Halfword operation indexing alignment Word opera...

Page 31: ...ng Final effective address Figure 9 Generation of Effective Virtual Address Indirect Real Extended Addressing The stack pointer doubJeword for push down instructions contains a 2O bit word address for...

Page 32: ...rrupt location is not an interrupt instruction if it is executed as the result of a program branch to the interrupt location under normal program control The only valid interrupt instructions are XPSD...

Page 33: ...on uses the 20 bit reference address as a real address except counter 4 with out indexing or mapping Interrupt Counter 4 uses the map if mapping is called for Access protect and write lock violations...

Page 34: ...n effect whenever the memory map is in effect PSWs 9 1 and the basic processor is operating in the slave mode PSWs 8 1 or in the master protected mode PSWs61 1 Access protection is not in effect when...

Page 35: ...memory page is unlocked write access to that page is permitted independent of the key value 28 Main Memory 2 A key value of 0000 is a skeleton key that will open any lock thus write access to any memo...

Page 36: ...ating point mode controls by executing either the LCFI or the LCF instruction Any program De gnaHon FuncHon FN cont can store the current state of the current floating point mode controls by executing...

Page 37: ...been achieved the basic processor stops executing the current program and executes the instruction in the cor responding interrupt location After the basic processor has successfully accessed the inte...

Page 38: ...y are disabled inhibited or both disabled and inhibited Generally if the enable disable flip flop is off level is disabled the interrupt level can undergo all state changes except that of moving from...

Page 39: ...es sor is a member When the processor bus becomes available and the b lsic processor is at an interruptible point the in terrupt system transmits the interrupt address to the basic processor It initia...

Page 40: ...3 21 optional 118 76 first 12 levels 22 119 77 23 120 78 24 121 79 25 122 7A 26 123 7B 27 88 58 Counter 1 zero 22 Counter 89 59 Counter 2 zero CI 0 23 Equals Zero 90 5A Counter 3 zero 24 91 5B Counter...

Page 41: ...r a PSS instruction The processor fault interrupt level is triggered by a signal when certain fault conditions are detected A POLR instruction must be used to reset the fault The memory fault interrup...

Page 42: ...state to the active state and the entire group is disabled removed from the interrupt recognition priority chain Consequently a waiting enabled interrupt level in an inhibited group does not prevent...

Page 43: ...e conditions apply as well as the following If the resultant value in the ef fective location is zero the corresponding counter equals zero interrupt is triggered 36 Trap System TRAP SYSTEM A trap is...

Page 44: ...etic AM For all instructions except DWand None overflow DH trap occurs after completion of instruction For DW and DH instruc tion is aborted with memory register CC1 CC3 and CC4 unchanged 68 44 Floati...

Page 45: ...asic processor detec TCC1 2 3 0 tion the PDFt flag wi II be set TCC4 0 if parity error on general reg ister or internal con trol regi ster TCC4 1 if other hardware errors 77 4D Instruction exception t...

Page 46: ...xecuted when the nonallowed operation is detected and to immediately execute the XPSD or PSS instruction in trap location X 40 A nonallowed operation cannot be masked NONEXISTENT INSTRUCTION Any instr...

Page 47: ...ry locations The virtual page address that caused the vio ation in the fouith PSW v oid The operation of the XPSD or PSS in trap location X 40 is as fol lows 1 Store the current PSWs 2 Store general r...

Page 48: ...remain at the value loaded from memory FIXED POINT OVERFLOW TRAP Overflow can occur for any of the following instructions Instruction Load Absolute Word Load Absolute Doubleword Mnemonic LAW LAD Opera...

Page 49: ...cates that the condition code bits are not af fected by the condition given under the Meaning heading 42 Trap System 2 If none of the above condi tions occurred but char acteristic underflow occurs wi...

Page 50: ...emory unit are given in Ap pendix C Table C 2 If the basic processor detects or receives a report of a hard ware error it attempts automatic retry of the current in struction If retry is unsuccessful...

Page 51: ...T FLAG The Processor Detected Fault PDF flag aids in solving a multiple error problem Most traps occur because of a dy namic programming consideration i e overflow attempted division by zero incorrect...

Page 52: ...FI LI MI Immediate type no operand access CALl CAL4 SF S WAIT RD WD RIO No operand access POLR POLP LRA Has operand access but traps are suppressed register bits and condition codes are set instead LB...

Page 53: ...ment value can be used to address any doubleword in main memory or in the current block of general registers The addressed doubleword is auto matica y located within doubleword storage boundaries The...

Page 54: ...ion of the instruction this field is used to modify the source address of an operand the destination ad dress of a result or both h Reserved fields In any format diagram that depi cts system inputs i...

Page 55: ...r more ex amples to illustrate the results of the instruction These examples are intended only to show how the in structions operate and not to demonstrate their full capabi iity Within the exampies h...

Page 56: ...G Gddi f th tr C i LI LOAD IMMEDIATE Immedi ate operand o I 2 LOAD IMMEDIATE extends the sign of the value field bit position 12 of the instruction word 12 bit positions to the left and then loads the...

Page 57: ...X 0123456789ABCDEF R xxxxxxxx X 01234567 CC xxxx xx10 50 Load Store Instructions Example 3 odd Rfield value Before execution After execution ED X 0000000012345678 X 0000000012345678 R xxxxxxxx X 00000...

Page 58: ...CC2 is set to 1 and the fixed point arithmetic trap mask AM is aI the BP traps to location X 43 after execution of LOAD ABSOLUTE WORD otherwise the BP executes the next instruction in sequence LCD LOA...

Page 59: ...t to 1 otherwise CC2 is reset to O Affected R Ru1 CC2 CC3 CC4 Trap Fixed point overflow IED1 32 _ 63 Ru1 IEDI O _ 31 R Condition code settings 2 3 4 Absolute value of effective doubleword 0 0 0 Zero o...

Page 60: ...set of words to be loaded begins with the word pointed to by the effective address of LM and the set of registers begins with register R The set of registers is treated modulo 16 i e the next registe...

Page 61: ...ctive byte into the floating round FR floating significance FS floating zero FZ and floating normalize FN mode control bits respectively however if bit 11 is 0 the FR FS FZ and FN control bits are not...

Page 62: ...E LECTNE Word index alignment After execution X 89ABCDEF89ABCDEP Register Ru 1 contains a 32 bit mask If R is an even value STORE SE LECTIVE stores the contents of register R into the effective word l...

Page 63: ...tus words into the effective byte location as follows Affected EBL PSWs 0_7 EBL ANALVZE INTERPRET INSTRUCTIONS ANLZ ANALYZE Word index alignment o 1 2 I I I I R X Reference address 7 8 10 11 12 13 14...

Page 64: ...is always per formed with an index register in the current register block if bits 12 14 of the analyzed instruction are nonzero During real extended addressing the effec tive virtual address of the an...

Page 65: ...2 Affected R CC Condition code settings 2 3 4 Instruction addressing type 0 0 0 Byte 0 0 Immediate byte 0 0 Halfword 0 0 Word 0 1 Immediate word 0 Doubleword 0 Direct addressing EWO 0 Indirect address...

Page 66: ...y for an add or subtract instruction there was no carry of a l bit out of the high order sign bit position of the result Carry for an add or subtract instruction there was a l bit carry out of the sig...

Page 67: ...index alignment ADD DOUBlEWORD adds the effective doubleword to the contents of registers Rand Ru1 treated as a single 64 bit register loads the 32 low order bits of the sum into reg ister Ru 1 and th...

Page 68: ...overflow Fixed point overflow o No carry from bit position 0 Carry from bit position 0 If CC2 is set to 1 and the fixed point arithmetic trap mask AM is a 1 the BP traps to location X 43 after loading...

Page 69: ...case the BP unconditionally aborts execution of the instruction at the time of operation code decoding and traps to location X 40 with the contents of register R register Ru 1 and the condition code...

Page 70: ...low 0 o Positive quotient no overflow Fixed point overflow If CC2 is set to 1 and the fixed point arithmetic trap mask AM is a 1 the BP traps to location XI 43 1 with the con tents of register R CC1 C...

Page 71: ...alue of the resultant byte This process allows modification of a byte by any number in the range 8 through 7 followed by a test If the value of the R field is zero the effective byte is tested for bei...

Page 72: ...time the memory unit containing the effecti ve location is reserved not accessible to other processors unti I the instruction is completed of the R field This word is added to the effective word and t...

Page 73: ...a nonexistent instruction in which case the basic processor uncondi tionally aborts execution of the instruction at the time of operation code decoding and then traps to location X 40 with the condit...

Page 74: ...ister doubleword less than effective doubleword a Register doubleword greater than effective doubleword CS COMPARE SELECTIVE COMPARE SE LECTIVE compares the contents of register R with the effective v...

Page 75: ...logical operations are performed bit by corresponding bit between two operands one operand is in register Rand 68 Logico I Instru ct ions the other operand is the effective word The result of the log...

Page 76: ...t reference memory Bit positions 15 20 and 24 of the effective virtual address are ignored Bit positions 21 22 and 23 of the effective virtual address determine the type of shift as follows 21 22 23 S...

Page 77: ...1 are shifted left C places Bits shifted past bit position 0 of register R are copied into bit position 31 of register Ru 1 No bits are lost If C is negative the contents of registers Rand Ru 1 are s...

Page 78: ...gister determine the direction and amount of the shift If indirect addressing and indexing are called for in the in struction bits 15 31 of the reference address are used to access the indirect word B...

Page 79: ...f the right shift operation the floating point result is loaded back into the general register s If the number was originally negative the twols complement of the resu Itant number is loaded into the...

Page 80: ...ition code settings 2 3 4 Resu It in R 0 0 Zero OBit 0 of register R is a 1 OBit 0 of register R is a 0 and bit positions 1 31 of register R contain at least one 1 o Sum is correct less than 2 Sum is...

Page 81: ...bit making each characteristic a 7 bit positive number 74 Floating Point Arithmetic Instructions for addition and subtraction an abnormal zero is treated the same as any nonzero operand 3 A positive...

Page 82: ...antee hardware and software identical results FR bit 4 of PSWs must be zero F Hexadecimal Value 1111 1111 1111 1111 7F FFFFFF 0000 0000 0000 0000 43 500000 0000 0000 0000 0000 3D Dl0000 1111 0000 0000...

Page 83: ...ero applies only if FN 0 FZ 0 FZ 1 If the final result of en addition or subtrac tion operation cannot be expressed in normal ized form because of the characteristic being reduced below zero underflow...

Page 84: ...c overflow occurs the basic processor always traps to location X 44 with the general registers unchanged and the condition code set to 0110 if the result is positive or to 0101 if the result is negati...

Page 85: ...ded into a set of internal registers FLOATING SUBTRACT SHORT forms the two s complement of the effective word and then operates identically to FLOATING ADD SH ORT FAS If no flo lting po n t arithmetic...

Page 86: ...s incremented If no floating point arithmetic fault occurs the quotient is loaded into register R as a short format floating point number Affected R CC R EW R Trap Floating point arith metic fault FDL...

Page 87: ...r real extended mode of addressing this is a 20 bit field 12 31 for real and virtual addressing modes it is a 17 bit field 15 31 80 Push Down Instructions Non Privi leged Bit position 32 of the SPD re...

Page 88: ...the contents of register Rinto the push down stack defined by the stack pointer doubleword located at the effective doubleword address of PSW If the push op eration can be successfully performed the...

Page 89: ...and the contents of this register become the contents of the new top of stack location 82 Push Down Instructi ons Non Privi Ieged If there is sufficient space in the stack for all of the specified reg...

Page 90: ...nd ending with the contents of the loca tion pointed to by the current top of stack address minus CC l 2 The current top of stack address is decremented by the value ofCC to point to the new top of st...

Page 91: ...Space count 0 word count O o o o 0 Space count 0 word count O o Space count 0 word count 0 __ 1 I VU I I v Instruction completed tFor real extended mode of addressing this is a 20 bit field 12 31 for...

Page 92: ...uring a PSS instruction the Space Count is decremented by 1 for each word pushed into the memory stack If the Space Count is decremented to a value of zero before all the words have been pushed the PS...

Page 93: ...18 10 19 9 20 8 21 7 22 6 23 5 24 25 PSW1 3 26 PSW2 2 27 PSW3 t 1 initial TSA 28 PSW4 initial TSA tAs a function of the hardware the contents of these 8 locations are in determinate after a PSS instr...

Page 94: ...essing If indirect addressing is specified the effective address is generated according to the rules for addressing then in effect as de scribed by the currently active PSWs Bit positions 9 and 10 mus...

Page 95: ...The new interrupt group inhibit bits CI 88 Push Down Instructions Privileged 11 EI are generated by ORing the old CI II EI bits with the contents of bits 37 38 and 39 of the PSWs as pulled from the m...

Page 96: ...word count O the ED is pulled from real memory locations 2 and 3 Status Stack Pointer Doubleword Only if initial Word Count 28 TSA 1 TSA until terminal TSA initial TSA 28 Word Count 1 Word Count unti...

Page 97: ...condition occurs the next instruction is accessed from the location pointed to by the effective address of the branch instruction 90 Execute Branch Instructions In the real extended addressing mode a...

Page 98: ...hen increments the contents of general register R by 1 If the result is a negative value the branch condition is satisfied and instruction execution then proceeds with the instruction pointed to by th...

Page 99: ...to location X 40 nonallowed operation trap In this case the instruction address stored by the XPSD instruction in location X 40 is the virtual ad dress of the aborted BAL instruction If the basic proc...

Page 100: ...k 15 31 IA Instruction address 32 35 WK Write key 37 CI Counter interrupt group inhibit 38 II I O interrupt group inhibit 39 EI External interrupt inhibit 58 59 RP Regi ster pointer 60 RA Register alt...

Page 101: ...T Addressing type All XPSDs The effective address of an XPSD instruction is generated in one of the following ways XPSD normal instruction When an XPSD instruction is encountered in the course of exec...

Page 102: ...s used as an in struction while the basic processor is in the slave or master protected mode CC 1 and CC3 are both set to lis if bit 9 of XPSD is a 1 the instruction address portion of the new program...

Page 103: ...ubleword if bit 8 of XPSD is a 0 the cur rent register pointer value remains unchanged Affected EDL PSWs If I 10 1 trap or interrupt instructions only effective address is subject to current active ad...

Page 104: ...bit positions 15 31 may be ignored insofar as the operation of the MMC instruction is concerned The results of the instruction are the same whether MMC is indirectly or directly addressed However if...

Page 105: ...eated as a circular set with the first register following the last thus a word count greater than 64 8 bit format or 128 ll bit format causes the first registers to be overwritten The initial value of...

Page 106: ...e word count is reduced to O When the loading process is completed the parameters con tained within registers Rand Ru1 have the following values Access protection control image address initial access...

Page 107: ...emented by one after the contents of each image word are loaded into the appro priate number of control registers The loading operation continues until the word count is reduced to zero At that time t...

Page 108: ...os as required Affected R CC Condition code settings 2 3 4 Results in R register o 0 No abnormal condition Address in R is real but for a nonexistent memory location 2 3 4 Results in R register o 0 Ad...

Page 109: ...0 Read status word 0 and clear o Reserved o Write double error stores an arbitrary word into a specified memory location with two differences compared to a normal Write Word instruction 1 Byte 3 in me...

Page 110: ...fter the WAIT instruction When the basic processor execution mode is changed from RUN mode to IDLE mode and back to RUN while the basic processor is waiting instruction execution proceeds with the nex...

Page 111: ...ster Address R 21 23 0 R O 20 and R 24 31 104 Control Instructions READ INTERRUPT INHIBITS The following configuration of RD can be used to read the contents of the interrupt inhibit field If the R fi...

Page 112: ...sensed according to the function code specified by bits 21 through 23 of the effective address of RD The codes and their associated functions are as follows Code Function 001 Read Armed or Waiting Sta...

Page 113: ...External Interrupt Group 2 Option Absent Not Assigned 22 External Interrupt Group 3 Option Absent Not Assigned 23 External Interrupt Group 4 Option Absent Not Assigned 24 External Interrupt Group 5 Op...

Page 114: ...fied element instead of the con tents of register 0 The specified element may return information to set the condition code 21 20 Configuration Information 0 0 Reserved 0 1 Reserved 1 0 Controller Clus...

Page 115: ...cessor SET ALARM INDICATOR The following configuration ofWDis used to set theALARM indicator on the maintenance section of the processor con trol panel 108 Contro I Instructions If the processor is in...

Page 116: ...l interrupt levels within the basi c processor interrupt system Bits 28 31 of the effective address specify the identification number see Table 11 of the group of interrupt levels to be controlled by...

Page 117: ...ther detai Is of I O instructions are illustrated in Figure 13 and de scribed in Table 13 110 Input Output Instructions 1 0 STATUS INFORMATION SIO TIO TDY AND HIO INSTRUCTIONS If the R field is coded...

Page 118: ...13 Description of I O Instructions Bit Applicable Instructions Position Mnemonics Function and or Description 0 All I O instructions If this bit is a 1 bits 15 31 of the initial I o instruction are mo...

Page 119: ...O instruction the required I O address may be compri sed of 1 a cluster address 2 a cluster address and a unit address 3 a cluster address a unit address and a device controller address or 4 a cluste...

Page 120: ...Status Information Register R Table 14 I O Status Information Register R cont Bit Position Significance Position Significance o Reserved t Bus Check Fault BCF This bit is set to 1 if a discrepancy exi...

Page 121: ...eadyll all device conditions re quired for proper operation are satisfied If bits 1 and 2 are 01 device IInot opera tional ll the addressed device has developed some condition that will not allow it t...

Page 122: ...An incorrect length condition is caused by a channel end or end of record condition occurring before the device controller has a count done signal from the lOP indicating that the byte count has been...

Page 123: ...occurri ng while the SIL flag is coded with a O An lOP halt condition causes the current operation to terminate immediately as an II unusua I endll This bit is set to a 1 if a Write Lock Violation WL...

Page 124: ...tion occurring before the device controller has a count done signal from the lOP indicating that Bit Position 8 cont 9 10 11 12 Table 18 lOP Status Byte cont Significance the byte count has been reduc...

Page 125: ...n reserved reserved START INPUT OUTPUT performs the following 1 Attempts to initiate an input or output operation whether an I o operation is started or not is dependent upon conditions within the add...

Page 126: ...rs is correct o 0 Not possible o 0 0 Not possible o 1 0 Pari ty error detected on returned status and or condition code The result of the SIO is indeterminate 2 3 4 Meaning o 0 I O address not recogni...

Page 127: ...120 Input Output Instructions TEST DEVICE is used to provide information about a de vice other than that obtained by means of the no in struction The operation of the selected lOP device controller a...

Page 128: ...rd does not affect bits 15 17 When indirect addressing is used the contents of the indirect address location bits 15 16 and 17 must specify the desired operation code extension If the Rfield is an odd...

Page 129: ...ions 21 23 may have values of X O X Unit ad dresses are required only if the cluster address is X O X 6 i e cluster contains either a BP and or MIOP Unit addresses X O X 5 may be assigned to processor...

Page 130: ...is coded as a 0 no I o interrupt is requested as a result of the byte count bei ng decremented to zero If two or more flags are coded to cause an interrupt for two or more conditions an interrupt is r...

Page 131: ...ible Parity error on returned status and or condition code The result of the Ala is indetermi nate o 0 1 0 Not possible 124 Input Output Instructions 2 3 4 Result of Ala o 1 0 Parity error detected on...

Page 132: ...the number and type of I O devices to be connected one or more of the following types of device controllers may be connected to n MIOP 1 Single unit device controller internal or external 2 MuIti unit...

Page 133: ...ng considerations the command list may be contained within one or more areas of memory and each area may be comprised of one or more I o command doublewords lOCOs 3 Command list continuity between lOC...

Page 134: ...O order are updated and the device controller device con tinue to operate as if the I o operation were defined by a single IOCD i e the data chain operation is transparent to the device controller de...

Page 135: ...operation 1 Memory Address Error MAE 2 lOP Control Error IOPCE 128 Input Output Processor lOP Fundamentals 3 Control Check Error CCF 4 lOP Memory Error IOPME 5 Bus Check Fault BCF whi Ie fetching an...

Page 136: ...memory uni t When the lOP receives a WLV signal the WLV bit within the status information register is set to 1 and remains set until a new VO operation is initiated within this I o sub channel by an...

Page 137: ...been punched The command address register within the I o subchannel is incremented by two by the chain modifier signal and the next consecutive 10CD within the command list is skipped over not fetched...

Page 138: ...device in an unpredictable state an RIO resets all controllers and devices on the addressed lOP As a result of accepting an SIO instruction a command ad dress register within the I O subchannel assig...

Page 139: ...ignored Other Control orders e g Rewind for a magnetic tape unit are listed and described in applic able Xerox peripheral equipment reference manuals 132 I O Operation Phases Depending upon the contro...

Page 140: ...ta or information Instead the lOP generates and loads zeros XIOOI into the data buffers of the appropriate I o subchannel and increments the memory byte address and decrements the byte count by one fo...

Page 141: ...SYSTEM RESET or I O RESET command is entered from the System Con trol Console SCC The progress of an 1 0 operation including the termination may be ascertained by evaluating the status information re...

Page 142: ...the same data paths Both consoles receive the same output either one of the consoles is selected for input by the ALTSEL switch on the Configuration Control Panel The communications rates of 10 or 30...

Page 143: ...system provides an advisory message following the com mand echo indicating the probable source of error A typi cal example of the display format is RSY EVENT A1 indicating that a reset command may no...

Page 144: ...lso displayed by indicators on the System Control Panel The SET SENSE SWITCHES command is always operative The sense switches may also be set by executing a WRITE DIRECT instruction see Chapter 3 The...

Page 145: ...ommands as well as the function described below 1 The system control processor bus interface is initialized 2 The processor memory bus and processor bus interfaces are initialized 3 The system memory...

Page 146: ...character is not in the allowed command set it is echoed followed by a question mark liN and no action results Valid commands are echoed the requested operation is then performed and a P Mode data di...

Page 147: ...cation or Q register for each Rcommand executed Actual contents of the memory or Q register location ref erenced by the shift instruction are not altered P Mode I INCREMENT REFERENCED ADDRESS AND DISP...

Page 148: ...CC printout in the format CE DDDDDDDD CC The CE field contains two hexadecimal digits that represent a cluster and an element address respectively The 8 digit D field displays the contents of the regi...

Page 149: ...causes 256 clocks to be issued The contents of the currently selected Single Clock Status Register are displayed The clock step counter is incremented by the number of clock steps specified by this c...

Page 150: ...red The P Mocle Repeat Mode may be reset by a CLEAR P MODE REPEAT MODE ZCMM3 a CLEAR MM FEATURES ZCMMO or a SUPER RESET ZCMM4 command The P Mode repeat feature is particularly useful for scan ning thr...

Page 151: ...hibit Mode is normally set to inhibit print out during execution of SCC functions which do not require a display 144 Control Commands The Display Inhibit Mode may be cleared by a CLEAR DISPLAY INHIBIT...

Page 152: ...value usually as a result of maintenance and or diagnostic activities see SET LOW CLOCK MARGINS and SET HIGH CLOCK MARGINS commands under Maintenance Control Commands POWER MARGIN This indicator is il...

Page 153: ...hen this switch is in the SCC position the alternate and remote i46 Controi Commands consoles may be connected in parallel with the System Control Console and may perform the same control func tions a...

Page 154: ...t to 1 so that an incorrect length in dication will not cause a Transmission Error Halt After the SIO instruction has been executed the basic processor executes a no instruction with the same effectiv...

Page 155: ...cription 0 Retry Inhibit If this bit is a 0 the basic processor will automatically retry the instruction which caused the trap to location X 4C if this bit is a 1 the basic processor is inhibited from...

Page 156: ...y cycles 2 1 Selects comparisons only during memory write cycle 0 Selects all memory cycle comparisons 3 1 Selects page comparisons 0 Selects word comparisons 4 1 System turns on audible alarm for 220...

Page 157: ...logic associated with each row of switches and indicators is located within each pro cessor cluster or memory unit itself Above each row is a marker strip that identifies the function of each switch...

Page 158: ...t bit designates the back panel location in the halves of the cabinet POWER POWER SYSTEM CLOCK NNORM ON SEL SEl Figure 16 Chassis Physical Configuration PROCESSOR I ADDRESS I BP MIOP 010 ENABLE ENABLE...

Page 159: ...r within a group of processor clusters Note The 5 bit chassis location number and not the proce ssor address is used in addressing the configuration switches for a given unit by the RD instruction dir...

Page 160: ...tion power to unit is off Determines to which central shared resources the reset signal is connected Selects which clock the memory shall use up position selects system c lock A down position selects...

Page 161: ...ry range 1 If all memory units have sizes that are powers of two they can a II be different they must however be assigned in order of decreasing size in the address continuum For instance three memory...

Page 162: ...of code are shown 1 the 8 bit Xerox Standard Computer Code i e the Extended Binary Coded Decimal Interchange Code EqCDIC 2 the 7 bit American National Standard Code for Information Interchange ANSCII...

Page 163: ...sed sets However Xerox software translates the characters into ANSCII characters as follows EBCDIC ANSCII 1 6 0 1 I 7 12 7 14 The EBCDIC cantrol codes in columns 0 and 1 and their binary representatio...

Page 164: ...feed or new line 16 22 SYN 11 9 6 1 6 sync 17 23 ETB 11 9 7 1 7 end of transmission block 18 24 CAN 11 9 8 1 8 cancel 19 25 EM 11 9 8 1 1 9 end of medium lA 26 SUB 11 9 8 2 1 10 substitute Replaces c...

Page 165: ...8 5 2 9 right parenthesis 5f 94 11 8 6 3 11 semicolon 5F 95 or 11 8 7 7 14 tilde or logical not 60 96 11 2 13 minus dash hyphen 61 97 0 1 2 15 slosh 62 98 11 0 9 2 62 through 69 wi II not be assigned...

Page 166: ...12 11 9 7 2 9A 154 12 11 8 2 9A through Al are unassigned 9B 155 12 11 8 3 9C 156 12 11 8 4 90 157 12 11 8 5 9E 158 12 11 8 6 9F 159 12 11 8 7 AO 160 11 0 8 1 Al 161 11 0 1 A2 162 s 11 0 2 7 3 A3 163...

Page 167: ...hrough DF wi II not be assigned DB 219 12 11 9 8 3 DC 220 12 11 9 8 4 DD 221 12 11 9 8 5 DE 222 12 11 9 8 6 DF 223 12 11 9 8 7 EO 224 0 8 2 EO El are unassigned El 225 11 0 9 1 E2 226 S 0 2 5 3 E3 227...

Page 168: ...1A 18 0 OE OF 10 11 12 13 14 15 16 17 18 19 1A 18 1C E OF 10 11 12 13 14 15 16 17 18 19 1A 18 1C 10 F 10 11 12 13 14 15 16 17 18 19 1A 18 1C 10 1E MULTIPLICATION TABLE 1 2 3 4 5 6 7 8 9 A 8 C 0 E F 2...

Page 169: ...46191 40625 x 10 8 0 23283 06436 53869 62891 x 10 9 0 14551 91522 83668 51807 x 10 10 0 90949 47017 72928 23792 x 10 12 0 56843 41886 08080 14870 x 10 13 0 35527 13678 80050 09294 x 10 14 0 22204 4604...

Page 170: ...s 14000 81 920 600 000 6 291 456 15000 86 016 700 000 7340032 Example Convert 0 89510 to its hexadecimal equivalent 16000 90 112 800 000 8388608 0 895 17000 94208 900 000 9437 184 18000 98304 AOO 000...

Page 171: ...0614 0615 0616 0617 0618 0619 0620 0621 0622 0623 270 0624 0625 0626 0627 0628 0629 0630 0631 0632 0633 0634 0635 0636 0637 0638 0639 280 0640 0641 0642 0643 0644 0645 0646 0647 0648 0649 0650 0651 06...

Page 172: ...1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 570 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 580 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 i4...

Page 173: ...2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 870 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 880 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 21...

Page 174: ...918 2919 2920 2921 2922 2923 2924 2925 2926 2927 B70 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 B80 2944 2945 2946 2947 2948 2949 2950 2951 2 1 1 2956 2957 2958 29...

Page 175: ...687 3688 3689 3690 3691 3692 3693 3694 3695 E70 3696 3697 3698 3699 3700 3701 3702 3703 3704 3705 3706 3707 3708 3709 3710 3711 E80 3712 3713 3714 3715 3716 3717 3718 3719 3720 3721 3722 3723 3724 372...

Page 176: ...00 00 00 6171875000 OE 00 00 00 86718 75000 IF 000000 1210937500 5F 00 00 00 3710937500 9F 00 00 00 62109 37500 OF 00 00 00 87109 37500 20 000000 12500 OOOQO 60 00 00 00 37500 00000 AO 00 00 00 62500...

Page 177: ...IE 00 00 00045 77636 00 5E 00 00 00143 43261 00 9E 00 00 00241 08886 00 DE 00 00 00338 74511 00 IF 00 00 00047 30224 00 5F 00 00 00144 95849 00 9F 00 00 00242 61474 00 OF 00 00 00340 27099 00 20 00 0...

Page 178: ...0 00000 56028 00 00 9E 00 00000 94175 00 00 DE 00 00001 32322 00 00 IF 00 00000 184n 00 00 5F 00 00000 56624 00 00 9F 00 00000 94nl 00 00 OF 00 00001 32918 00 00 20 00 00000 19073 00 00 60 00 00000 57...

Page 179: ...00 00 DO 00000 00514 00 00 00 IE 00000 00069 00 00 00 5E 00000 00218 00 00 00 9E 00000 00367 00 00 00 DE 00000 00516 00 00 00 IF 00000 00072 00 00 00 5F 00000 00221 00 00 00 9F 00000 00370 00 00 00 OF...

Page 180: ...7 4 88 355 328 47 0 000 000 000 000 007 105 427 357 601 001 858 711 242 675 781 25 281 474 976 710 656 48 0 000 000 000 000 003 552 713 678 800 500 929 355 621 337 890 625 562 9 9 953 21 312 49 0 000...

Page 181: ...tion or EHl 174 Appendix B Term EHl EI ESA EVA EW EWl FN FR FS FZ Meaning Effective halfword location halfword loca tion pointed to by effective virtual address of an instruction for halfword operatio...

Page 182: ...ield capable of directly addressing any general register in current register block by using a value in range 0 15 or any word in main memory in address range 16 through 131 071 This address value is i...

Page 183: ...truction word In instruction word if X 0 no indexing is performed 176 Appendix B Term X cont X n Meaning if X f 0 indexing is performed after indirect addressing if indirect addressing is called for w...

Page 184: ...Out In indicatort Reserved Multiple error Reserved MIE 8 24 Processor interface Control Memory Reserved Control Memory Reserved sequence check fault Fault CMF Fault CMF address bit 0 address bit 0 9 2...

Page 185: ...snapshot 22 Reserved 23 Memory unit parity error 24 Storage module selection error 25 Address In parity error 26 Data In parity error 27 Write lock memory storage parity error 28 Port selection error...

Page 186: ...ered DWell o Well Organized o Clear III ustrated o Reference o Maintaining 0 Operating What is your overall rating of this publication What is your occupation o Very Good o Fair o Very Poor o Good o P...

Page 187: ...old BUSINESS REPLY MAIL No postage stamp necessary if mailed in the United States Postage will be paid by Xerox Corporation 701 South Aviation Boulevard EI Segundo California 90245 vldtJle First Class...

Page 188: ...701 South Aviation Boulevard EI Segundo California 90245 213679 4511 XEROX XEROX is a trademark of XEROX CORPORATION...

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