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Preliminary Rev. 0.3 11/10

Copyright © 2010 by Silicon Laboratories

Si5324

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

S i 5 3 2 4

A

N Y

- F

R E Q U E N C Y

P

R E C I S I O N

C

L O C K

M

U L T I P L I E R

/ J

I T T E R

A

T T E N U A T O R

Features



Generates any frequency from 2 kHz to 945 MHz
and select frequencies to 1.4 GHz from an input
frequency of 2 kHz to 710 MHz



Ultra-low jitter clock outputs as low as 290 fs rms
(12 kHz–20 MHz), 320 fs rms (50 kHz–80 MHz)



Integrated loop filter with selectable loop bandwidth
(4– 525 Hz)



Meets ITU-T G.8251 and Telcordia GR-253-CORE
jitter specification



Hitless input clock switching with phase build-out



Freerun, Digital Hold operation



Configurable signal format per output (LVPECL,
LVDS, CML, CMOS)



Support for ITU G.709 and custom FEC ratios
(255/238, 255/237, 255/236, 239/237, 66/64,
239/238, 15/14, 253/221, 255/238)



LOL, LOS, FOS alarm outputs



I

2

C or SPI programmable



On-chip voltage regulator with high PSNR



Single supply 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%



Small size: 6 x 6 mm 36-lead QFN

Applications



Broadcast video –3G/HD/SD-SDI, Genlock



Packet Optical Transport Systems (P-OTS), MSPP



OTN OTU-1/2/3/4 Asynchronous Demapping
(Gapped Clock)



SONET OC-48/192/768, SDH/STM-16/64/256 line
cards



1/2/4/8/10G Fibre Channel line cards



GbE/10/40/100G Synchronous Ethernet
(LAN/WAN)



Data converter clocking



Wireless base stations



Test and measurement

Description

The Si5324 is a low-bandwidth, jitter-attenuating, precision clock multiplier for applications requiring sub 1 ps jitter
performance with loop bandwidths between 4 Hz and 525 Hz. The Si5324 accepts two input clocks ranging from
2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz to 945 MHz and select frequencies to
1.4 GHz. The two outputs are divided down separately from a common source. The Si5324 can also use its
external reference as a clock source for frequency synthesis. The device provides virtually any frequency
translation combination across this operating range. The Si5324 input clock frequency and clock multiplication ratio
are programmable via an I

2

C or SPI interface. The Si5324 is based on Silicon Laboratories' 3rd-generation

DSPLL

®

technology, which provides any-frequency synthesis and jitter attenuation in a highly integrated PLL

solution that eliminates the need for external VCXO and filter components. The DSPLL loop bandwidth is digitally
programmable, providing jitter performance optimization at the application level. The Si5324 is ideal for providing
clock multiplication and jitter attenuation in high performance timing applications.

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Summary of Contents for SI5324

Page 1: ...k SONET OC 48 192 768 SDH STM 16 64 256 line cards 1 2 4 8 10G Fibre Channel line cards GbE 10 40 100G Synchronous Ethernet LAN WAN Data converter clocking Wireless base stations Test and measurement Description The Si5324 is a low bandwidth jitter attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance with loop bandwidths between 4 Hz and 525 Hz The Si5324 a...

Page 2: ... DSPLL Loss of Signal Frequency Offset Xtal or Refclock CKOUT2 CKIN1 CKOUT1 CKIN2 N31 N2 NC1_LS NC2_LS Skew Adjust Signal Detect Device Interrupt VDD 1 8 2 5 or 3 3 V GND N32 Loss of Lock Clock Select I2 C SPI Port Control Rate Select N1_HS Xtal Refclock ...

Page 3: ...3 Functional Description 11 3 1 External Reference 12 3 2 Additional Documentation 12 4 Pin Descriptions Si5324 13 5 Register Map 17 6 Register Descriptions 19 6 1 ICAL 52 7 Ordering Guide 53 8 Package Outline 36 Pin QFN 55 9 Recommended PCB Layout 56 10 Si5324 Device Top Mark 58 Document Change List 59 Contact Information 60 ...

Page 4: ... PLL divider settings for a given input frequency clock multi plication ratio combination 0 002 710 MHz Output Clock Frequency CKOUT1 CKOUT2 CKOF 0 002 970 1213 945 1134 1400 MHz 3 Level Input Pins RATE0 and RATE1 Input Mid Current IIMM See Note 2 2 2 µA Input Clocks CKIN1 CKIN2 Differential Voltage Swing CKNDPP 0 25 VPP Common Mode Voltage CKNVCM 1 8 V 5 0 9 1 4 V 2 5 V 10 1 0 1 7 V 3 3 V 10 1 1 ...

Page 5: ...320 450 fs rms Jitter Peaking JPK 0 1 dB Phase Noise CKOPN 100 Hz offset 95 dBc Hz 1 kHz offset 110 dBc Hz 10 kHz offset 117 dBc Hz 100 kHz offset 118 dBc Hz 1 MHz offset 131 dBc Hz Spurious Noise SPSPUR Max spur n x F3 n 1 n x F3 100 MHz 67 dBc Package Thermal Resistance Junction to Ambient JA Still Air 32 ºC W Thermal Resistance Case to Ambient JC Still Air 14 ºC W Table 1 Performance Specificat...

Page 6: ...55 150 ºC ESD HBM Tolerance 100 pF 1 5 k All pins except CKIN CKIN 2 kV ESD MM Tolerance All pins except CKIN CKIN 150 V ESD HBM Tolerance 100 pF 1 5 k CKIN CKIN 750 V ESD MM Tolerance CKIN CKIN 100 V Latch up Tolerance JESD78 Compliant Note Permanent device damage may occur if the Absolute Maximum Ratings are exceeded Functional operation should be restricted to the conditions as specified in the...

Page 7: ...Si5324 Preliminary Rev 0 3 7 2 Typical Phase Noise Performance Figure 1 Broadcast Video Jitter Bandwidth Jitter peak peak Jitter RMS 10 Hz to 20 MHz 5 24 ps 484 Note Number of samples 8 91E9 ...

Page 8: ...r Bandwidth Jitter RMS SONET_OC48 12 kHz to 20 MHz 266 fs SONET_OC192_A 20 kHz to 80 MHz 283 fs SONET_OC192_B 4 MHz to 80 MHz 155 fs SONET_OC192_C 50 kHz to 80 MHz 275 fs Brick Wall_800 Hz to 80 MHz 287 fs Note Jitter integration bands include low pass 20 dB Dec and hi pass 60 dB Dec roll offs per Telecordia GR 253 CORE ...

Page 9: ...Si5324 Preliminary Rev 0 3 9 Figure 3 Wireless Base Station Phase Noise Jitter Bandwidth Jitter peak peak Jitter RMS 10 Hz to 20 MHz 7 28 ps 581 Note Number of samples 8 91E9 ...

Page 10: ...1 µF RATE 1 0 2 Crystal Ref Clk Rate VDD 15 k 15 k XA XB Crystal Option 1 Input Clock Sources CKIN2 CKIN2 130 130 82 82 VDD 3 3 V 130 130 82 82 VDD 3 3 V CKIN1 CKIN1 GND PAD Si5324 RST CKOUT1 CKOUT1 VDD GND Ferrite Bead System Power Supply C1 C2 C3 Reset Clock Outputs CKOUT2 CKOUT2 CMODE Control Mode H CKIN2 CKIN2 100 0 1 µF 0 1 µF 100 0 1 µF 0 1 µF C4 0 1 µF 0 1 µF 0 1 µF 1 µF CKIN1 CKIN1 INT_C1B...

Page 11: ... be used to calculate valid loop bandwidth settings for a given input clock frequency clock multiplication ratio The Si5324 supports hitless switching between the two synchronous input clocks in compliance with Telcordia GR 253 CORE that greatly minimizes the propagation of phase transients to the clock outputs during an input clock transition maximum 200 ps phase change Manual and automatic rever...

Page 12: ...in the DSPLL This external reference is required for the device to perform jitter attenuation Specific recommendations can be found in the Family Reference Manual In digital hold the DSPLL remains locked and tracks the external reference Note that crystals can have temperature sensitivities Due to the low bandwidth capabilities of this part any low frequency wander or instability on the external r...

Page 13: ...ons as a maskable interrupt output with active polarity con trolled by the INT_POL register bit If used as an alarm output the pin functions as a LOS and option ally FOS alarm indicator for CKIN1 Set CK1_BAD_PIN 1 and INT_PIN 0 0 CKIN1 present 1 LOS FOS on CKIN1 The active polarity is controlled by CK_BAD_POL If no function is selected the pin tristates 4 C2B O LVCMOS CKIN2 Invalid Indicator This ...

Page 14: ...ernal crystal or reference clock to be applied to the XA XB port Refer to the Family Reference Manual for settings These pins have both a weak pull up and a weak pull down they default to M L setting corresponds to ground M setting corresponds to VDD 2 H setting corresponds to VDD Some designs may require an external resistor voltage divider when driven by an active device that will tri state 16 1...

Page 15: ... LVCMOS Serial Clock This pin functions as the serial clock input for both SPI and I2 C modes This pin has a weak pull down 23 SDA_SDO I O LVCMOS Serial Data In I2 C control mode CMODE 0 this pin functions as the bidirec tional serial data port In SPI control mode CMODE 1 this pin functions as the serial data output 25 24 A1 A0 I LVCMOS Serial Port Address In I2 C control mode CMODE 0 these pins f...

Page 16: ...kHz to 1 4175 GHz Output signal format is selected by SFOUT2_REG register bits Output is differential for LVPECL LVDS and CML compatible modes For CMOS format both output pins drive identi cal single ended clock outputs 36 CMODE I LVCMOS Control Mode Selects I2 C or SPI control mode for the Si5324 0 I2C Control Mode 1 SPI Control Mode This pin must not be NC Tie either high or low GND PAD GND GND ...

Page 17: ...EL_REG 3 0 3 CKSEL_REG 1 0 DHOLD SQ_ICAL 4 AUTOSEL_REG 1 0 HST_DEL 4 0 5 ICMOS 1 0 6 SLEEP SFOUT2_REG 2 0 SFOUT1_REG 2 0 7 FOSREFSEL 2 0 8 HLOG_2 1 0 HLOG_1 1 0 9 HIST_AVG 4 0 10 DSBL2_ REG DSBL1_ REG 11 PD_CK2 PD_CK1 19 FOS_EN FOS_THR 1 0 VALTIME 1 0 LOCK T2 0 20 CK2_BAD_PIN CK1_ BAD_ PIN LOL_PIN INT_PIN 21 CK1_ACTV_PIN CKSEL_PIN 22 CK_ACTV_ POL CK_BAD_ POL LOL_POL INT_POL 23 LOS2_MSK LOS1_MSK LO...

Page 18: ... 137 FASTLOCK 138 LOS2_EN 1 1 LOS1_EN 1 1 139 LOS2_EN 0 0 LOS1_EN 0 0 FOS2_EN FOS1_EN 142 INDEPENDENTSKEW1 7 0 143 INDEPENDENTSKEW2 7 0 185 NVM_REVID 7 0 Table 3 CKOUT_ALWAYS_ON and SQ_ICAL Truth Table CKOUT_ALWAYS_ON SQ_ICAL Results 0 0 CKOUT OFF until after the first ICAL 0 1 CKOUT OFF until after the first successful ICAL i e when LOL is low 1 0 CKOUT always ON including during an ICAL 1 1 CKOU...

Page 19: ...utput will be available even if SQ_ICAL is on and ICAL is not complete or successful See Table 3 on page 18 0 Squelch output until part is calibrated ICAL 1 Provide an output Notes 1 The frequency may be significantly off until the part is calibrated 2 Must be 1 to control output to output skew 4 2 Reserved Reserved 1 BYPASS_ REG Bypass Register This bit enables or disables the PLL bypass mode Use...

Page 20: ...ty 01 CKIN2 is 2nd priority 10 Reserved 11 Reserved 1 0 CK_PRIOR1 1 0 CK_PRIOR 1 Selects which of the input clocks will be 1st priority in the autoselection state machine 00 CKIN1 is 1st priority 01 CKIN2 is 1st priority 10 Reserved 11 Reserved Register 2 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name BWSEL_REG 3 0 Reserved Type R W R Bit Name Function 7 4 BWSEL_REG 3 0 BWSEL_REG Selects nominal f3dB bandwidth ...

Page 21: ...ntinues to control clock selection and CKSEL_REG is of no consequence 00 CKIN_1 selected 01 CKIN_2 selected 10 Reserved 11 Reserved 5 DHOLD DHOLD Forces the part into digital hold This bit overrides all other manual and automatic clock selection controls 0 Normal operation 1 Force digital hold mode Overrides all other settings and ignores the quality of all of the input clocks 4 SQ_ICAL SQ_ICAL Th...

Page 22: ...ic Revertive 11 Reserved 5 Reserved Reserved 4 0 HIST_DEL 4 0 HIST_DEL 4 0 Selects amount of delay to be used in generating the history information used for Digital Hold Register 5 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name ICMOS 1 0 Reserved Type R W R Bit Name Function 7 6 ICMOS 1 0 ICMOS 1 0 When the output buffer is set to CMOS mode these bits determine the output buffer drive strength The first number ...

Page 23: ... rides the SFOUTn_REG 2 0 output signal format settings 0 Normal operation 1 Sleep mode 5 3 SFOUT2_ REG 2 0 SFOUT2_REG 2 0 Controls output signal format and disable for CKOUT2 output buffer Bypass mode is not supported for CMOS output clocks 000 Reserved 001 Disable 010 CMOS 011 Low swing LVDS 100 Reserved 101 LVPECL 110 CML 111 LVDS 2 0 SFOUT1_ REG 2 0 SFOUT1_REG 2 0 Controls output signal format...

Page 24: ... FOSREFSEL 2 0 Type R R W Bit Name Function 7 3 Reserved Reserved 2 0 FOSREFSEL 2 0 FOSREFSEL 2 0 Selects which input clock is used as the reference frequency for Frequency Off Set FOS alarms 000 XA XB External reference 001 CKIN1 010 CKIN2 011 Reserved 100 Reserved 101 Reserved 110 Reserved 111 Reserved ...

Page 25: ... will occur without glitches or runt pulses 11 Reserved 5 4 HLOG_1 1 0 HLOG_1 1 0 00 Normal operation 01 Holds CKOUT1 output at static logic 0 Entrance and exit from this state will occur without glitches or runt pulses 10 Holds CKOUT1 output at static logic 1 Entrance and exit from this state will occur without glitches or runt pulses 11 Reserved 3 0 Reserved Reserved Register 9 Bit D7 D6 D5 D4 D...

Page 26: ...OUT2 enabled 1 CKOUT2 disabled 2 DSBL1_REG DSBL1_REG This bit controls the powerdown of the CKOUT1 output buffer If disable mode is selected the NC1 output divider is also powered down 0 CKOUT1 enabled 1 CKOUT1 disabled 1 0 Reserved Reserved Register 11 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name Reserved PD_CK2 PD_CK1 Type R R W R W Bit Name Function 7 2 Reserved Reserved 1 PD_CK2 PD_CK2 This bit controls t...

Page 27: ... with a Stratum 3 3E used for REFCLK 01 48 to 49 ppm SMC 10 30 ppm SONET Minimum Clock SMC with a Stratum 3 3E used for REFCLK 11 200 ppm 4 3 VALTIME 1 0 VALTIME 1 0 Sets amount of time for input clock to be valid before the associated alarm is removed 00 2 ms 01 100 ms 10 200 ms 11 13 seconds 2 0 LOCKT 2 0 LOCKT 2 0 Sets retrigger interval for one shot monitoring phase detector output One shot is...

Page 28: ..._BAD_PIN CK1_BAD_PIN The CK1_BAD status can be reflected on the C1B output pin 0 C1B output pin tristated 1 C1B status reflected to output pin 1 LOL_PIN LOL_PIN The LOL_INT status bit can be reflected on the LOL output pin 0 LOL output pin tristated 1 LOL_INT status reflected to output pin 0 INT_PIN INT_PIN Reflects the interrupt status on the INT_C1B output pin 0 Interrupt status not displayed on...

Page 29: ..._ACTV_PIN enable function CK1_ACTV_PIN is of consequence only when pin controlled clock selection is being used 0 CS_CA output pin tristated 1 Clock Active status reflected to output pin 0 CKSEL_PIN CKSEL_PIN If manual clock selection is being used clock selection can be controlled via the CKSEL_REG 1 0 register bits or the CS_CA input pin This bit is only active when AUTOSEL_REG Manual 0 CS_CA pi...

Page 30: ... CS_CA signals when reflected on an output pin 0 Active low 1 Active high 2 CK_BAD_ POL CK_BAD_POL Sets the active polarity for the INT_C1B and C2B signals when reflected on output pins 0 Active low 1 Active high 1 LOL_POL LOL_POL Sets the active polarity for the LOL status when reflected on an output pin 0 Active low 1 Active high 0 INT_POL INT_POL Sets the active polarity for the interrupt statu...

Page 31: ...1 LOS2_FLG ignored in generating interrupt output 1 LOS1_MSK LOS1_MSK Determines if a LOS on CKIN1 LOS1_FLG is used in the generation of an interrupt Writes to this register do not change the value held in the LOS1_FLG register 0 LOS1 alarm triggers active interrupt on INT_C1B output if INT_PIN 1 1 LOS1_FLG ignored in generating interrupt output 0 LOSX_MSK LOSX_MSK Determines if a LOS on XA XB LOS...

Page 32: ..._PIN 1 1 FOS2_FLG ignored in generating interrupt output 1 FOS1_MSK FOS1_MSK Determines if the FOS1_FLG is used in the generation of an interrupt Writes to this reg ister do not change the value held in the FOS1_FLG register 0 FOS1 alarm triggers active interrupt on INT_C1B output if INT_PIN 1 1 FOS1_FLG ignored in generating interrupt output 0 LOL_MSK LOL_MSK Determines if the LOL_FLG is used in ...

Page 33: ...000 N1 4 001 N1 5 010 N1 6 011 N1 7 100 N1 8 101 N1 9 110 N1 10 111 N1 11 4 0 Reserved Reserved Register 31 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name Reserved NC1_LS 19 16 Type R R W Bit Name Function 7 4 Reserved Reserved 3 0 NC1_LS 19 16 NC1_LS 19 16 Sets value for NC1 low speed divider which drives CKOUT1 output Must be 0 or odd 00000000000000000000 1 00000000000000000001 2 00000000000000000011 4 000000...

Page 34: ...0000000 1 00000000000000000001 2 00000000000000000011 4 00000000000000000101 6 11111111111111111111 2 20 Valid divider values 1 2 4 6 2 20 Register 33 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name NC1_LS 7 0 Type R W Bit Name Function 7 0 NC1_LS 19 0 NC1_LS 7 0 Sets value for NC1 low speed divider which drives CKOUT1 output Must be 0 or odd 00000000000000000000 1 00000000000000000001 2 00000000000000000011 4 0...

Page 35: ...odd 00000000000000000000 1 00000000000000000001 2 00000000000000000011 4 00000000000000000101 6 11111111111111111111 2 20 Valid divider values 1 2 4 6 2 20 Register 35 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name NC2_LS 15 8 Type R W Bit Name Function 7 0 NC2_LS 15 8 NC2_LS 15 8 Sets value for NC2 low speed divider which drives CKOUT2 output Must be 0 or odd 00000000000000000000 1 00000000000000000001 2 00000...

Page 36: ...e NC2_LS 7 0 Type R W Bit Name Function 7 0 NC2_LS 7 0 NC2_LS 7 0 Sets value for NC2 low speed divider which drives CKOUT2 output Must be 0 or odd 00000000000000000000 1 00000000000000000001 2 00000000000000000011 4 00000000000000000101 6 11111111111111111111 220 Valid divider values 1 2 4 6 220 ...

Page 37: ...2 0 N2_HS 2 0 Sets value for N2 high speed divider which drives N2LS low speed divider 000 4 001 5 010 6 011 7 100 8 101 9 110 10 111 11 4 Reserved Reserved 3 0 N2_LS 19 16 N2_LS 19 16 Sets value for N2 low speed divider which drives phase detector 00000000000000000001 2 00000000000000000011 4 00000000000000000101 6 11111111111111111111 220 Valid divider values 2 4 6 220 ...

Page 38: ...phase detector 00000000000000000001 2 00000000000000000011 4 00000000000000000101 6 11111111111111111111 220 Valid divider values 2 4 6 220 Register 42 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name N2_LS 7 0 Type R W Bit Name Function 7 0 N2_LS 7 0 N2_LS 7 0 Sets value for N2 low speed divider which drives phase detector 00000000000000000001 2 00000000000000000011 4 00000000000000000101 6 11111111111111111111 ...

Page 39: ...value for input divider for CKIN1 0000000000000000000 1 0000000000000000001 2 0000000000000000010 3 1111111111111111111 219 Valid divider values 1 2 3 219 Register 44 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name N31_ 15 8 Type R W Bit Name Function 7 0 N31_ 15 8 N31_ 15 8 Sets value for input divider for CKIN1 0000000000000000000 1 0000000000000000001 2 0000000000000000010 3 1111111111111111111 219 Valid divi...

Page 40: ...00000000000000000 1 0000000000000000001 2 0000000000000000010 3 1111111111111111111 219 Valid divider values 1 2 3 219 Register 46 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name Reserved N32_ 18 16 Type R R W Bit Name Function 7 3 Reserved Reserved 2 0 N32_ 18 16 N32_ 18 16 Sets value for input divider for CKIN1 0000000000000000000 1 0000000000000000001 2 0000000000000000010 3 1111111111111111111 219 Valid divi...

Page 41: ... divider for CKIN1 0000000000000000000 1 0000000000000000001 2 0000000000000000010 3 1111111111111111111 219 Valid divider values 1 2 3 219 Register 48 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name N32_ 7 0 Type R W Bit Name Function 7 0 N32_ 7 0 N32_ 7 0 Sets value for input divider for CKIN1 0000000000000000000 1 0000000000000000001 2 0000000000000000010 3 1111111111111111111 219 Valid divider values 1 2 3 2...

Page 42: ...CLKIN2RATE 2 0 CLKIN2RATE_ 2 0 CKINn frequency selection for FOS alarm monitoring 000 10 27 MHz 001 25 54 MHz 002 50 105 MHz 003 95 215 MHz 004 190 435 MHz 005 375 710 MHz 006 Reserved 007 Reserved 2 0 CLKIN1RATE 2 0 CLKIN1RATE 2 0 CKINn frequency selection for FOS alarm monitoring 000 10 27 MHz 001 25 54 MHz 002 50 105 MHz 003 95 215 MHz 004 190 435 MHz 005 375 710 MHz 006 Reserved 007 Reserved ...

Page 43: ...e clock for the PLL input 0 CKIN1 is not the active input clock Either it is not selected or LOS1_INT is 1 1 CKIN1 is the active input clock Register 129 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name Reserved LOS2_INT LOS1_INT LOSX_INT Type R R R R Bit Name Function 7 3 Reserved Reserved 2 LOS2_INT LOS2_INT Indicates the LOS status on CKIN2 0 Normal operation 1 Internal loss of signal alarm on CKIN2 input 1 LO...

Page 44: ...s 0 Indicates digital hold history registers have not been filled The digital hold output frequency may not meet specifications 1 Indicates digital hold history registers have been filled The digital hold output frequency is valid 7 5 3 Reserved Reserved 2 FOS2_INT CKIN2 Frequency Offset Status 0 Normal operation 1 Internal frequency offset alarm on CKIN2 input 1 FOS1_INT CKIN1 Frequency Offset St...

Page 45: ...ot masked by LOS2_MSK bit Flag cleared by writing 0 to this bit 1 LOS1_FLG CKIN1 Loss of Signal Flag 0 Normal operation 1 Held version of LOS1_INT Generates active output interrupt if output interrupt pin is enabled INT_PIN 1 and if not masked by LOS1_MSK bit Flag cleared by writing 0 to this bit 0 LOSX_FLG External Reference signal on pins XA XB Loss of Signal Flag 0 Normal operation 1 Held versi...

Page 46: ...is enabled INT_PIN 1 and if not masked by FOS2_MSK bit Flag cleared by writing 0 to this bit 2 FOS1_FLG CLKIN_1 Frequency Offset Flag 0 Normal operation 1 Held version of FOS1_INT Generates active output interrupt if output interrupt pin is enabled INT_PIN 1 and if not masked by FOS1_MSK bit Flag cleared by writing 0 to this bit 1 LOL_FLG PLL Loss of Lock Flag 0 PLL locked 1 Held version of LOL_IN...

Page 47: ...Name Function 7 0 PARTNUM_RO 11 0 Device ID 1 of 2 0000 0001 1000 Si5324 Others Reserved Register 135 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name PARTNUM_RO 3 0 REVID_RO 3 0 Type R R Bit Name Function 7 4 PARTNUM_RO 11 0 Device ID 2 of 2 0000 0001 1000 Si5324 Others Reserved 3 0 REVID_RO 3 0 Indicates Revision Number of Device 0010 Revision C Others Reserved ...

Page 48: ...reset 6 ICAL Start an Internal Calibration Sequence For proper operation the device must go through an internal calibration sequence ICAL is a self clearing bit Writing a one to this location initiates an ICAL The calibra tion is complete once the LOL alarm goes low A valid stable clock within 100 ppm must be present to begin ICAL Note Any divider CLKINn_RATE or BWSEL_REG changes require an ICAL t...

Page 49: ...Function 7 2 Reserved Reserved 1 LOS2_EN 1 0 Enable CKIN2 LOS Monitoring on the Specified Input 2 of 2 Note LOS2_EN is split between two registers 00 Disable LOS monitoring 01 Reserved 10 Enable LOSA monitoring 11 Enable LOS monitoring LOSA is a slower and less sensitive version of LOS See the Family Reference Manual for details 0 LOS1_EN 1 0 Enable CKIN1 LOS Monitoring on the Specified Input 1 of...

Page 50: ...11 Enable LOS monitoring LOSA is a slower and less sensitive version of LOS See the family reference manual for details 4 LOS_EN 1 0 Enable CKIN1 LOS Monitoring on the Specified Input 1 of 2 Note LOS1_EN is split between two registers 00 Disable LOS monitoring 01 Reserved 10 Enable LOSA monitoring 11 Enable LOS monitoring LOSA is a slower and less sensitive version of LOS See the family reference ...

Page 51: ...mplement of the phase offset in terms of clocks from the high speed output divider Default 0 Register 143 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name INDEPENDENTSKEW2 7 0 Type R W Bit Name Function 7 0 INDEPENDENTSKEW2 7 0 INDEPENDENTSKEW2 8 bit field that represents a twos complement of the phase offset in terms of clocks from the high speed output divider Default 0 Register 185 Bit D7 D6 D5 D4 D3 D2 D1 D0 ...

Page 52: ...for details In addition after a successful calibration operation changing any of the Registers indicated in Table 4 requires that a calibration be performed again by the same procedure writing a 1 to bit D6 in register 136 Table 4 ICAL Sensitive Registers Address Register 0 BYPASS_REG 0 CKOUT_ALWAYS_ON 1 CK_PRIOR1 1 CK_PRIOR2 2 BWSEL_REG 4 HIST_DEL 5 ICMOS 7 FOSREFSEL 9 HIST_AVG 10 DSBL1_REG 10 DS...

Page 53: ...A C GM 2 kHz 945 MHz 970 1134 MHz 1 213 1 417 GHz 36 Lead 6 x 6 mm QFN Yes 40 to 85 C Si5324B C GM 2 kHz 808 MHz 36 Lead 6 x 6 mm QFN Yes 40 to 85 C Si5324C C GM 2 kHz 346 MHz 36 Lead 6 x 6 mm QFN Yes 40 to 85 C Si5324D C GM 2 kHz 150 MHz 36 Lead 6 x 6 mm QFN Yes 40 to 85 C Note Add an R at the end of the device to denote tape and reel options ...

Page 54: ...Si53152 2 2 644 644 0 6 ps rms typ Si53163 2 1 707 710 0 3 ps rms typ Si53173 1 2 710 710 0 3 ps rms typ Si53193 1 1 710 1400 0 3 ps rms typ Si53233 2 2 707 1050 0 3 ps rms typ Si53263 2 2 710 1400 0 3 ps rms typ Si53663 4 5 707 1050 0 3 ps rms typ Si53683 4 5 710 1400 0 3 ps rms typ Any Frequency Precision Clock Jitter Attenuation Low Bandwidth 4 to 525 Hz Si5324 2 2 710 1400 0 29 ps rms typ Note...

Page 55: ... Max Min Nom Max A 0 80 0 85 0 90 L 0 50 0 60 0 70 A1 0 00 0 02 0 05 12º b 0 18 0 25 0 30 aaa 0 10 D 6 00 BSC bbb 0 10 D2 3 95 4 10 4 25 ccc 0 08 e 0 50 BSC ddd 0 10 E 6 00 BSC eee 0 05 E2 3 95 4 10 4 25 Notes 1 All dimensions shown are in millimeters mm unless otherwise noted 2 Dimensioning and Tolerancing per ANSI Y14 5M 1994 3 This drawing conforms to JEDEC outline MO 220 variation VJJD 4 Recom...

Page 56: ...Si5324 56 Preliminary Rev 0 3 9 Recommended PCB Layout Figure 8 PCB Land Pattern Diagram Figure 9 Ground Pad Recommended Layout ...

Page 57: ... mm Notes Solder Mask Design 1 All metal pads are to be non solder mask defined NSMD Clearance between the solder mask and the metal pad is to be 60 µm minimum all the way around the pad Notes Stencil Design 1 A stainless steel laser cut and electro polished stencil with trapezoidal walls should be used to assure good solder paste release 2 The stencil thickness should be 0 125 mm 5 mils 3 The rat...

Page 58: ...ee Ordering Guide for options Line 2 Marking C GM C Product Revision G Temperature Range 40 to 85 C RoHS6 M QFN Package Line 3 Marking YYWWRF YY Year WW Work Week R Die Revision F Internal code Assigned by the Assembly House Corresponds to the year and work week of the mold date Line 4 Marking Pin 1 Identifier Circle 0 75 mm Diameter Lower Left Justified XXXX Internal Code ...

Page 59: ...ote to register CKOUT_ALWAYS_ON on how to control output to output skew Added Product Selection Guide to Section 7 Ordering Guide Corrected typographical errors in Table 1 Updated typical phase noise performance page Updated functional description Added additional phase noise plots to Section 2 Typical Phase Noise Performance Updated Register Map Revised Device Top Mark Revision 0 25 to Revision 0...

Page 60: ...ed herein Additionally Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters Silicon Laboratories reserves the right to make changes without further notice Silicon Laboratories makes no warranty rep resentation or guarantee regarding the suitability of its products for any particular purpose nor does Silicon Laboratories assume any liability arisi...

Page 61: ...ectronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Silicon Laboratories SI5324A C GMR SI5324B C GMR SI5324D C GMR Si5324A C GM Si5324B C GM Si5324C C GM Si5324D C GM ...

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