Redpine Signals RS9110-N-11-02 Integration Manual Download

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Redpine Signals, Inc. Proprietary and Confidential

RS9110-N-11-02

Module Integration Guide

September 26

2011

Redpine Signals, Inc

2107 N. First Street, #680

San Jose, CA 95131.

Tel: (408) 748-3385

Fax: (408) 705-2019

Email:

[email protected]

Website:

www.redpinesignals.com

Summary of Contents for RS9110-N-11-02

Page 1: ... RS9110 N 11 02 Module Integration Guide V Ve er rs si io on n 1 1 3 39 9 September 26th 2011 Redpine Signals Inc 2107 N First Street 680 San Jose CA 95131 Tel 408 748 3385 Fax 408 705 2019 Email info redpinesignals com Website www redpinesignals com ...

Page 2: ...G Gu ui id de e V Ve er rs si io on n 1 1 3 39 9 About this Document The RS9110 N 11 02 is an 802 11n single stream module with built in MAC BBP RF and PA and front end components It interfaces to a host processor through an SDIO or SPI interface This document provides information that may be used while integrating the module into an end solution ...

Page 3: ... Integration 7 2 2 SPI Interface Integration 8 3 Recommended RS9110 N 11 02 PCB Landing Pattern 10 4 Circuit and Layout Guidelines 11 5 Chip Antenna Layout Recommendations 13 5 1 Antenna Matching Network 14 6 Reference Oscillator Specifications 16 6 1 List of Recommended Crystal Oscillators 17 7 Recommended Specifications for Schottky Diode 18 7 1 Recommended Parts 18 8 Sample Layout 19 8 1 Layer ...

Page 4: ...HOST_WAKEUP_INT UART1_OUT UART1_IN UART2_OUT VMOD C4 10uF 802 11bgn WLAN Module C12 22uF CASE B VDD_EXT C7 10uF CASE B RESET_n C9 0 1uF VIN33 RESET Circuitry R7 100K CLK_REF Make TXC OE 1 GND 2 OUT 3 VDD 4 U1 7C40000192 C1 2 2uF XTAL_EN XTAL_EN XTAL_EN XTAL_EN R1 33E VRF28 1 1 2 2 FB1 BEAD Reference Clock Circuitry TP1 Place Z1 Z3 Close together and near to ANT1 SDIO_CLK SDIO_DATA1 SDIO_DATA3 SDIO...

Page 5: ...EF_CLK 14 PSPI_CSN1 46 SLEEP_CLK_X1 35 SLEEP_CLK_X2 34 I2C_SCL 6 I2C_SDA 7 GND 30 GND 26 RESETn 15 NC 41 WLAN_ACTIVE 31 BT_PRIORITY 29 SLEEP_CLK_IN 32 HOST_WAKEUP_INT 53 NC 42 VRF33 43 VRF33 44 SDIO_DATA3 SD3 13 SDIO_DATA2 SPI_INTR 12 SDIO_DATA1 SPI_MISO 11 SDIO_DATA0 SPI_MOSI 10 SDIO_CMD SPI_CS 9 SDIO_CLK SPI_CLK 8 GPIO_1 55 GND 16 VINBCKDC 27 VINLDOP123 39 FBDC1P3 38 VOUTBCKDC1P3 37 UART2_IN 36 ...

Page 6: ...si io on n 1 1 3 39 9 NOTE on SPI_CS and SPI_CLK Based on the Host SPI configuration during BOOT UP SPI Master could be coming up as GPIO pins In the wake of this possibility it may be needed to add a pull up on the SPI_CS and a pull up CPOL 1 pull down CPOL 0 on the SPI_CLK The value of pull up pull down resistor should follow the recommendations as given on the HOST side ...

Page 7: ...61A106KE19L 6 1 C7 10uF CAP TANTALUM 10UF 6 3V 10 SMD CASE B AVX TAJB106K006RNJ 7 1 C12 22uF CAP TANTALUM 22UF 6 3V 20 SMD CASE B Kemet B45196H1226M209 RESISTORS 8 2 R1 R25 33E CHIP RES 33R 5 200PPM 0402 1 10W 0402 Panasonic ERJ 2GEJ330X 9 1 R3 820E CHIP RES 820R 5 200PPM 0402 1 10W 0402 Panasonic ERJ 2GEJ821X 10 3 R4 R5 R6 1K RES 1 0K OHM 1 16W 5 0402 SMD 0402 Yageo RC0402JR 071KL 11 1 R7 100K CH...

Page 8: ...ntegration Item Qty Reference Part Value Description Jedec Mfg Part No CAPACITORS 1 1 C5 8 2pF CER CHP C 8 2P 0 25P C0G 0402 25V LF 0402 Murata GRM1555C1H8R2CZ01D 2 4 C3 C8 C11 C13 0 1uF CER CHIP C 0 1U 10 X5R 0402 6 3V 0402 Murata GRM155R61A104KA01D 3 1 C1 2 2uF CER CHIP C 2 2U 20 X5R 0402 4V 0402 Murata GRM155R60G225ME15D 4 1 C6 1uF CAP CER 1 0UF 16V 10 X7R 0805 0805 Murata GRM21BR71C105KA01L 5 ...

Page 9: ...scription in the schematic Sample part number for Z1 given here Murata GRM1555C1H8R2CZ01D IC S 17 1 U1 40MHz Crystal Oscillator TXC 7C40000192 18 1 U2 RS9110 N 11 02 802 11bgn WLAN Module Redpine RS9110 N 11 02 19 1 ANT1 Antenna 2 45GHz SMD Antenna Antenna Factor ANT 2 45 CHP T 20 1 J1 5X2 Box Header Burg Header 21 1 J2 Microwave Coaxial Connector with switch Murata MM8430 2610RA1 NO POPULATE 22 2...

Page 10: ...Confidential Page 10 R RS S9 91 11 10 0 N N 1 11 1 0 02 2 M Mo od du ul le e I In nt te eg gr ra at ti io on n G Gu ui id de e V Ve er rs si io on n 1 1 3 39 9 3 Recommended RS9110 N 11 02 PCB Landing Pattern Figure 3 PCB Landing Pattern ...

Page 11: ...he RESET can be Host driven At the time of Power on Please ensure that the reset is held low for at least 20mSec After this the reset should be driven high b Reset may be driven by an R C circuit The recommended value of R is 100 Kohms and the recommended value of C is 0 1uF 3 The reference schematics shown in the previous section include the recommended power supply filtering and decoupling 4 The...

Page 12: ...nfidential Page 12 R RS S9 91 11 10 0 N N 1 11 1 0 02 2 M Mo od du ul le e I In nt te eg gr ra at ti io on n G Gu ui id de e V Ve er rs si io on n 1 1 3 39 9 8 The design of the embedded system should provide for a peak power load of 325mA ...

Page 13: ...antenna Please follow the rules listed in the picture below while doing the layout for the chip Antenna Removing the ground plane from the underneath the antenna is very important Figure 4 Antenna layout The chosen Chip Antennae are λ 4 antennae and would require external ground plane for proper functioning and the length of the ground plane behind the antenna from the feedpoint of antenna to back...

Page 14: ...round plane configuration 2 Distance from antenna 3 Topology around antenna 4 Feed point transmission line impedance 5 Trace width 6 Trace length 7 Matching Network 8 PCB substrate thickness 9 PCB substrate dielectric constant 5 1 Antenna Matching Network Provision should be given for a pie network as shown in the schematics The values shown below are just for example The values of the pie network...

Page 15: ...ra at ti io on n G Gu ui id de e V Ve er rs si io on n 1 1 3 39 9 L 3nHto3 9nH C 1 5pFto3pF C 1 5pFto3pF L 3nHto3 9nH Ground Plane RF IN ANT Ground Plane RF IN ANT Figure 5 Antenna Matching Network Note The radiation pattern of the Antenna can be studied in an Anechoic Chamber using a Network Analyzer a Horn Standard Gain Antenna ...

Page 16: ...rational temperature at rated voltage Supply Voltage VDD 2 8 10 or 3 3 10 V Power supply should ideally be locally regulated and with adequate filtering Power Supply PSRR 60 dB Operational Temperature 40 to 85 C For industrial grade products Output Voltage 0 level 10 of VDD V Output Voltage 1 level 90 of VDD V Output type Square Wave Duty cycle 45 to 55 Rise time Fall time 10 ns Periodic Jitter 30...

Page 17: ...Recommended Crystal Oscillators 1 TXC part number 7C40000192 This part was used for characterizing all our boards The following can also be used based on the specifications 2 Ecera part number FD4000113 3 Fox Xpresso part number FXO HC538R 4 Kyocera part number KC25200C40C3KE00 5 Tai Saw Technology part number TW0377E 6 Epson Toyocom SG 150 SCE 7 Epson Toyocom SG 211 SCE 8 Golledge GXO 5332L E 40 ...

Page 18: ...In nt te eg gr ra at ti io on n G Gu ui id de e V Ve er rs si io on n 1 1 3 39 9 7 Recommended Specifications for Schottky Diode Forward voltage VFM 0 40 V max Average forward current IF AV 3 0 A Repetitive peak reverse voltage VRRM 30 V 7 1 Recommended Parts a Toshiba part number CMS02 b NXP part number PMEG3030BEP ...

Page 19: ...M Mo od du ul le e I In nt te eg gr ra at ti io on n G Gu ui id de e V Ve er rs si io on n 1 1 3 39 9 8 Sample Layout This section provides a sample layout of a board that instantiates RS9110 N 11 02 This reference board is an SDIO module with a standard interface into an SDIO slot 8 1 Top Layer ...

Page 20: ...ignals Inc Proprietary and Confidential Page 20 R RS S9 91 11 10 0 N N 1 11 1 0 02 2 M Mo od du ul le e I In nt te eg gr ra at ti io on n G Gu ui id de e V Ve er rs si io on n 1 1 3 39 9 8 1 Layer 2 8 2 Layer 3 ...

Page 21: ...nc Proprietary and Confidential Page 21 R RS S9 91 11 10 0 N N 1 11 1 0 02 2 M Mo od du ul le e I In nt te eg gr ra at ti io on n G Gu ui id de e V Ve er rs si io on n 1 1 3 39 9 8 3 Bottom Layer 8 4 Component Placement ...

Page 22: ...nnected to ground through a zero ohm resistor SD0_WP signal has to be connected to ground through a 10K resistor 2 Drive 3 3V voltage to Redpine module from the output of a power gate or regulator which is controlled with SD0_PWR as shown in the below circuit SDIO stack on windows operating system controls the SD0 PWR signal and is the output of application processor As shown below 3 3V Main is un...

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