Realtek RTL8212 Layout Manual Download | Manualshive

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6/9-PORT 10/100/1000MBPS SWITCH CONTROLLER

and 10/100/1000 DUAL ETHERNET TRANSCEIVER

LAYOUT GUIDE

Rev. 1.1

29 August 2005

Track ID: JATR-1076-21

RTL8366/8369 &
RTL8212

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Summary of Contents for RTL8212

Page 1: ...6 9 PORT 10 100 1000MBPS SWITCH CONTROLLER and 10 100 1000 DUAL ETHERNET TRANSCEIVER LAYOUT GUIDE Rev 1 1 29 August 2005 Track ID JATR 1076 21 RTL8366 8369 RTL8212 ...

Page 2: ...of any kind neither expressed nor implied including but not limited to the particular purpose Realtek may make improvements and or changes in this document or in the product described in this document at any time This document could include technical inaccuracies or typographical errors USING THIS DOCUMENT Though every effort has been made to ensure that this document is current and accurate more ...

Page 3: ...IGURE 1 LONG TRACE LAYOUT FOR RSGMII 6 FIGURE 2 TRACE WIDTH AND SPACING RECOMMENDATION FOR MICROSTRIP 7 FIGURE 3 SYMMETRICAL ROUTING 7 FIGURE 4 SYMMETRICAL ROUTING INTO AC CAPS 8 FIGURE 5 RSGMII LAYOUT REFERENCE 8 FIGURE 6 MDI DIFFERENTIAL LAYOUT REFERENCE 9 FIGURE 7 SEPARATE SERDES GND AND SYSTEM GND VIAA BEAD 10 FIGURE 8 RTL8212 COMPONENT SIDE FOOTPRINT 10 FIGURE 9 RTL8212 SOLDER SIDE FOOTPRINT ...

Page 4: ...M for packet buffering non blocking switch fabric internal register management and an embedded 8051 into a single 0 15µm CMOS device Only a 25MHz crystal is required an optional EEPROM is offered for internal register configuration The 6 9th port of the RTL8366 8369 implements a GMII MII RGMII interface for connecting with an external PHY or MAC in specific applications This interface could be con...

Page 5: ... components such as clock source and transformer to meet the application requirements Keep power and ground noise levels below 100mV Use bulk capacitors 4 7uF 10uF between each power and ground plane Use 0 1uF decoupling capacitors to reduce high frequency noise on the power and ground planes Keep decoupling capacitors as close as possible to the RTL8366 8369 and RTL8212 Fill in unused areas of co...

Page 6: ...es of a differential pair should be 5 mil wide with 7 mil wide air gap spacing between the traces of the pair Spacing to all non Serdes signals should be at least 30 mil in order to avoid harmful coupling issues Trace routes over long distances should be routed at an off angle to the X Y axis of a PCB layer to distribute the effects of fiberglass bundle weaves and resin rich areas of the dielectri...

Page 7: ...pair routing lengths as short as possible Match the length of both sets of the differential pairs allowing no more than a 5 mil delta between the lengths of the two signals Length matching should occur on a segment by segment basis vs across the total distance of the overall route Differential pairs should have a continuous reference plane and avoid vias Size 0402 AC coupling capacitors are strong...

Page 8: ...ide 8 Track ID JATR 1076 21 Rev 1 1 AC CapPads Preferred Capplacement is insamelocation symmetric Avoid Capplacementis notinsamelocation symmetric Figure 4 Symmetrical Routing Into AC Caps RSGMII layout reference is shown in Figure 5 Figure 5 RSGMII Layout Reference ...

Page 9: ...e at 60Ω 6 All microstrip traces of a differential pair should be 5 mil wide with a 7 mil wide air gap spacing between the trace of the pair Keep differential pairs as close as possible and route both traces as identically as possible meaning width length and location Avoid vias and layer change if possible MDI Differential layout reference is show in Figure 6 Figure 6 MDI Differential Layout Refe...

Page 10: ...212 QFN76 Bead Figure 7 Separate Serdes GND and System GND via a Bead Use multi vias drill size 20 24 mil in the RTL8212 footprint and fill in large areas of component side and solder side with solid copper Then attach them with vias to the ground plane in order to reduce the temperature of the PCB The following figures are examples of an RTL8212 footprint Figure 8 RTL8212 Component Side Footprint...

Page 11: ...rystal or OSC component Don t let the clock trace pass over a gap in the ground plane 3 4 Power Planes When designing a 4 layer PCB layout divide the power plane into 3 3V_MAC 3 3V_PHY 1 8V and 1 2V Use 0 1µF decoupling capacitors and bulk capacitors between each power plane and ground plane 3 5 Ground Planes Keep the system ground region as one continuous unbroken plane that extends from the prim...

Page 12: ...5014 Bothhand GS5014 and Lankom LG4803S A 10 100 1000Base T UTP application circuit with transformer is show in Figure 10 1 2 3 4 5 6 7 8 RJ45 RTL8212 MDIDN MDIDP MDICN MDICP MDIBN MDIBP MDIAN MDIAP 0 1uF 0 1uF 0 1uF 0 1uF 75ohm 75ohm 75ohm 75ohm 1000pF 2KV Figure 10 UTP Application Circuit with Transformer Realtek Semiconductor Corp Headquarters No 2 Industry East Road IX Science based Industrial...

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