Oki MSM9225B User Manual Download

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MSM9225B

User’s Manual

CAN (Controller Area Network) Controller

Oki Electric Industry Co., Ltd.

Ver. 4.0

July 2001

FEUL9225B-04

Summary of Contents for MSM9225B

Page 1: ...MSM9225B User s Manual CAN Controller Area Network Controller Oki Electric Industry Co Ltd Ver 4 0 July 2001 FEUL9225B 04 1...

Page 2: ...and intellectual property right etc is granted by us in connection with the use of the product and or the information and drawings contained herein No responsibility is assumed by us for any infringem...

Page 3: ...ler which conforms to the CAN protocol specification Bosch V2 0 part B Active In this manual additions and modifications that have been made on the upgrade to the MSM9225B from the MSM9225 are indicat...

Page 4: ...aracteristics L level 0 level Indicates low voltage signal levels VIL and VOL as specified by the electrical characteristics Register description Read write attribute R indicates a readable bit and W...

Page 5: ...S 1Ehex 2 21 2 4 4 CAN Bus Timing Register 0 BTR0 1Fhex 2 21 2 4 5 CAN Bus Timing Register 1 BTR1 2Ehex 2 23 2 4 6 Communication Input Output Control Register TIOC 2Fhex 2 27 2 4 7 Group Message Regis...

Page 6: ...rectly Connected to Bus Transceiver PCA82C250 4 7 4 3 2 3 Monitoring the CAN Bus 4 8 Chapter 5 Electrical Characteristics 5 1 Electrical Characteristics 5 1 5 1 1 Absolute Maximum Ratings 5 1 5 1 2 Re...

Page 7: ...Chapter 1 Overview...

Page 8: ...flag is provided Priority control by identifier 2032 types in standard format 2032 218 types in extended format Microcontroller interface Corresponding to both parallel and serial interface Parallel...

Page 9: ...window Suspension CAN CAN Bus Power steering CAN Figure 1 2 Configuration Example B Rx0 Tx0 Tx1 Rx1 VDD GND Bit stream logic BSL Transmission control logic TCL Error management logic EML Bit timing l...

Page 10: ...w B B 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 A4 A5 A6 A7 SDO GND SDI SCLK PRD W SR CS INT AD2 D2 AD1 D1 AD0 D0 Mode1 Mode0 GND PALE PWR RESET V DD T 1 X 34 35 36 37 38 39 40 41 42 43...

Page 11: ...and data is captured beginning with the second byte of data input from the SDI pin PALE 27 I Address latch signal pin When at a H level addresses are captured If used in the parallel mode and the addr...

Page 12: ...set pin System is reset when this pin is at a L level XT 13 I XT 14 O Clock pins If internal oscillator is used connect a crystal ceramic resonator If external clock is used input clock via XT pin The...

Page 13: ...Chapter 2 Register Descriptions...

Page 14: ...d format or a 5 byte extended format identifier and a message of a maximum of 8 bytes can be stored in each message box The control registers are selected by the low order 4 bits Ehex Fhex of the addr...

Page 15: ...4EH GMSK00 Message mask register 00 4FH GMSK01 Message mask register 01 5EH GMSK02 Message mask register 02 5FH GMSK03 Message mask register 03 6EH GMSK10 Message mask register 10 6FH GMSK11 Message...

Page 16: ...fier stored in a message box the data of the message is stored in the corresponding message box in the message memory Set the highest message box number to be used in the register NMES see Section 2 4...

Page 17: ...ing the transmission completion interrupt request flag ITF is disabled 1 Setting the transmission completion interrupt request flag ITF is enabled 0 Setting the receive completion interrupt request fl...

Page 18: ...mitted received A message of a frame type other than the specified frame type cannot be transmitted received Table 2 2 shows the relationship between setting and frame type At reset the FRM bit is set...

Page 19: ...sure to write a 1 to the MMA bit before writing to a message box from the microcontroller Then read the MMA bit If 1 is read the message box is accessible If 0 is read write a 1 in a loop until the MM...

Page 20: ...identifier field ID28 to ID18 for standard format and ID28 to ID0 for extended format is overwritten with the received message s identifier when the message box for which the group message function ha...

Page 21: ...e bits are undefined 2 3 4 Identifiers 2 3 4 Messages 0 7 MSG0 7 in the case of standard format IDR2 4 TMSG0 7 in the case of extended format x3 to xDhex In the case of the standard format IDFM 0 the...

Page 22: ...0 bit 6 for standard format 0 1 ID17 for extended format message 0 bit 7 for standard format Figure 2 5 Identifier 2 Message 0 IDR2 MSG0 The top rows indicate the ID for the extended format setting a...

Page 23: ...essage 2 bit 7 for standard format Write 0 to the unused bits Figure 2 7 Identifier 4 Message 2 IDR4 MSG2 The top rows indicate the content of message 0 for the extended format setting and the bottom...

Page 24: ...dard format 0 1 Message 1 bit 7 for extended format message 4 bit 7 for standard format Figure 2 9 Message 1 Message 4 TMSG1 MSG4 The top rows indicate the content of message 2 for the extended format...

Page 25: ...ard format 0 1 Message 3 bit 7 for extended format message 6 bit 7 for standard format Figure 2 11 Message 3 Message 6 TMSG3 MSG6 The top rows indicate the content of message 4 for the extended format...

Page 26: ...tting 0 1 Message 5 bit 6 for extended format setting 0 1 Message 5 bit 7 for extended format setting Figure 2 13 Message 5 TMSG5 The content of message 6 for the extended format setting is shown belo...

Page 27: ...ndefined Undefined Undefined Undefined Undefined 0 1 Message 7 bit 0 for extended format setting 0 1 Message 7 bit 1 for extended format setting 0 1 Message 7 bit 2 for extended format setting 0 1 Mes...

Page 28: ...re transmitted sequentially from the smaller message box number 2 Receive operation Data is always written to the message box with the smallest message box number and never written to other message bo...

Page 29: ...4EH GMSK00 Message mask register 00 00hex R W 4FH GMSK01 Message mask register 01 00hex R W 5EH GMSK02 Message mask register 02 00hex R W 5FH GMSK03 Message mask register 03 00hex Bits 0 to 2 are not...

Page 30: ...alization mode of the communication control section At the time of initialization start the initialization after writing a 1 to INIT and reading it to ensure that INIT has been set to 1 Also at the en...

Page 31: ...mission Failure of MSM9225B for transmission operation 3 Bit synchronization SYNC This bit is used to set the bit synchronization edge to synchronize at the CAN bus When SYNC is 0 the synchronization...

Page 32: ...upt generated 0 Output to the interrupt output pin is disabled 1 Output to the interrupt output pin is enabled ITF IRF and IEF are in the read only state when they are 1 1 cannot be written Figure 2 1...

Page 33: ...ten to this bit At reset IRF is set to 0 6 Error interrupt request flag IEF IEF becomes 1 when an error occurs Only 0 can be written to this bit At reset IEF is set to 0 7 Master interrupt control ena...

Page 34: ...e 2 21 Message Box Count Setting Register NMES 2 4 4 CAN Bus Timing Register 0 BTR0 1Fhex The MSM9225B has an internal baud rate prescaler that generates the BTL Bit Timing Logic signal by dividing th...

Page 35: ...At reset BRP5 to BRP0 are set to 000000 Table 2 5 BTL Cycle Time Setting BRP5 BRP4 BRP3 BRP2 BRP0 BRP0 BTL cycle time 0 0 0 0 0 0 1 System clock period 0 0 0 0 0 1 2 System clock period 1 1 1 1 1 0 63...

Page 36: ...L cycle 1 1 1 1 16 BTL cycle TSEG22 TSEG21 TSEG20 TSEG2 0 0 0 1 BTL cycle 0 0 1 2 BTL cycle 1 1 0 7 BTL cycle 1 1 1 8 BTL cycle Unused bit Write a 0 Figure 2 23 CAN Bus Timing Register 1 BTR1 1 Time s...

Page 37: ...bus and the input buffer Set so as to wait until ACK is returned before the start of phase segment 1 Period of prop segment time output buffer delay CAN bus delay input buffer delay Phase segment 1 2...

Page 38: ...SJW2 TSEG2 SYNC SJW1 TSEG1 SJW2 SYNC SJW1 TSEG1 TSEG2 SJW2 CAN bus signal Before resynchronization After resynchronization When an edge is detected in the period of SJW the internal bit status is shif...

Page 39: ...W SJW1 Sampling Point Sampling Point Sampling Point Sampling Point a If an edge lies before the sampling point SYNC SJW1 TSEG1 TSEG2 SYNC SJW1 TSEG1 TSEG2 SJW2 CAN bus signal Before resynchronization...

Page 40: ...B 0CTP1 0CTN1 0CPOL1 0CTP0 0CTN0 0CPOL0 0CMD1 0CMD0 LSB TIOC 2Fhex R W R W Initial value 0 0 0 0 0 0 0 0 0CMD1 0CMD0 Output mode of Tx0 Tx1 Input mode of Rx0 Rx1 0 0 0 1 Disabled 1 0 Single phase mode...

Page 41: ...content and input output mode At reset OCMD1 to OCMD0 are set to 00 Table 2 9 Input output Mode Setting OCMD1 OCMD0 Output mode of Tx0 and Tx1 Input mode of Rx0 Rx1 0 0 0 1 Disabled 1 0 Single phase m...

Page 42: ...tween bit content and output driver format Output control circuit Output data Synchronization clock VDD Pch Tx0 Nch GND VDD Pch Tx1 Nch GND Figure 2 28 Circuit Configuration of Output Driver Table 2 1...

Page 43: ...se identifier unmasked identifier set in the identifier field has the high priority The group message function can be set for two message boxes The group message function is valid when the EGM0 EGM1 b...

Page 44: ...0 0 0 0 0 0 MSB M0ID20 M0ID19 M0ID18 M0ID17 M0ID16 M0ID15 M0ID14 M0ID13 LSB GMSK01 4Fhex R W R W Initial value 0 0 0 0 0 0 0 0 MSB M0ID12 M0ID11 M0ID10 M0ID9 M0ID8 M0ID7 M0ID6 M0ID5 LSB GMSK02 5Ehex R...

Page 45: ...r and 1110 EH message box number respectively In this case it is also possible to set GMR03 to GMR00 to E message box number and GMR13 to GMR10 to F message box number Figure 2 31 b shows an example o...

Page 46: ...ontents of the message memory and control registers are held but the oscillator and all circuits stop to save power consumption Access to from external units is therefore disabled Stop mode is termina...

Page 47: ...ff release start operation When this bit is 0 the bus off state will be released if 11 consecutive recessive bits have been received 128 times since the time immediately after the bus off state was en...

Page 48: ...TRSN0 Message box number 0 0 0 0 0 0 0 0 1 1 1 1 1 0 E 1 1 1 1 F Unused bit When it is read the value is undefined Figure 2 34 Communication Message Box Number Register TMN 1 Communication message box...

Page 49: ...er CANS 1 Receive Error Warning REW When the Receive Error Counter REC 96 REW becomes 1 If REW 1 it is probable that the bus has been damaged Testing the bus for this condition is recommended At reset...

Page 50: ...ates the BOFF value of the CAN status register CANS 9Fhex bit 7 indicates the TEP value of CANS 7 1 BOFF Bus off state 6 0 1 5 4 3 2 1 0 Transmit Error Counter TEC AEhex Error active state Error passi...

Page 51: ...ANS2 BEhex R W R W Initial 0 0 0 0 0 0 0 0 value 0 Bit error does not occur 1 Bit error occurs 0 Stuff error does not occur 1 Stuff error occurs 0 Acknowledgment error does not occur 1 Acknowledgment...

Page 52: ...microcontroller does not access the CANS register during the period from the time the bus off state is entered to the time it is released the microcontroller cannot detect whether the CAN controller h...

Page 53: ...Chapter 3 Operational Description...

Page 54: ...bit INIT 1 Set the number of message boxes with the NMES register 1Ehex Set the message control register x0hex Set message boxes Set FRM DCL3 DCL0 ID28 ID0 All message settings complete Set the interr...

Page 55: ...A 0 and TRQ 1 Set TIRS bit of CANC register 0Ehex to 1 YES NO Since the MMA bit cannot be set to 1 while message boxes are being accessed from the CAN side read and verify its value Transmit setting c...

Page 56: ...0 Read receive data from message box Message control register s RCS 0 CANC register s 0Ehex CANA 0 Receive complete YES NO YES CANI register s 0Fhex IRF 1 NO Check whether new receive data has been wr...

Page 57: ...valid message boxes that can be rewritten Start rewrite Set MMA bit of message control register x0hex to 1 Read MMA bit MMA 1 Rewrite FRM DLC3 DLC0 ID28 ID0 Set MMA bit of message control register to...

Page 58: ...ethod automatically transmits preset message data in message box Table 3 1 lists the settings of the message control register Table 3 1 Message Control Register Settings for Automatic Response Bit Sym...

Page 59: ...o 0 Data frame transmission Transmission completion generates interrupt INT pin H to L Set ITF bit to 0 Set RSC bit of message control register to 0 Transmit data setting Remote reception and transmis...

Page 60: ...ration Table 3 2 Message Control Register Settings for Manual Response Bit Symbol Value Comments Bit 5 TRQ 0 Set to receive message box Bit 3 EIR 1 Set interrupt to verify remote frame reception Bit 2...

Page 61: ...age control register to 1 Set MMA 0 and TRQ 1 message control register bits Set TIRS bit of CANC register 0Ehex to 1 Transmission completion generates interrupt INT pin H to L Write transmit data to m...

Page 62: ...Chapter 4 Microcontroller Interface...

Page 63: ...ures the address in an internal register When 8 SCLK clocks are received the MSM9225B loads the address into the internal address counter and waits for data reception Next input data to the SDI pin An...

Page 64: ...rite address 1 Internal processing interval Data write address 1 A0 A1 A2 A3 A4 A5 A6 A7 SDI SCLK CS SR W SWAIT Address reception Data transmission Internal processing interval Data transmission Data...

Page 65: ...el Interface The following three types of parallel interfaces are available 1 Address data separate bus type no address latch signal 2 Address data separate bus type with address latch signal 3 Multip...

Page 66: ...ontroller INT CS PALE PRD SRW PWR PRDY SWAIT A7 0 AD7 0 D7 0 SDO SDI SCLK RESET XT XT Mode1 Mode0 INT CS RD WR WAIT A7 0 D7 0 RESET 11 10 27 9 26 16 4 1 44 41 38 31 5 7 8 25 Reset signal 30 29 If the...

Page 67: ...CSTCV16M0X51Q 10 k 5 pF Ceramic resonator of Murata MFG CSTCV16M0X11Q is recommended 125 kbps Figure 4 3 Address Data Separate Bus With Address Latch Signal 4 3 1 3 Address Data Multiplexed Bus MSM922...

Page 68: ...PRDY SWAIT A7 0 AD7 0 D7 0 SDO SDI XT XT R W WAIT RESET 11 10 27 9 26 16 4 1 44 41 38 31 5 7 8 25 Reset signal 13 14 30 29 10 k 5 V RESET Mode0 SCLK Mode1 SDIN SDOUT SCLK Open CLK If the built in osc...

Page 69: ...O P CATH 4 Open 1 Open 3 GND 5 E 7 VCC 8 2 ANODE 1 4 4 1 Open Open 6 2 8 7 5 3 6N137 GND 2 CANL 6 CAN BUS LINE 5 V 6 Figure 4 6 Electrically Isolated from Bus Transceiver PCA82C250 4 3 2 2 Directly Co...

Page 70: ...3 2 3 Monitoring the CAN Bus MSM9225B 23 Open PCA82C252 CANH 11 CANL 12 CAN BUS LINE VCC 10 GND 13 RTH 8 RTL 9 RxD 3 INH 1 TxD 2 EN 6 NERR 4 STB 5 Port Port Port T 0 T 1 R 0 22 18 R 1 19 Battery 5 V...

Page 71: ...Chapter 5 Electrical Characteristics...

Page 72: ...nit Power Supply Voltage VDD Ta 25 C 0 3 to 7 0 V Input Voltage VI 0 3 to VDD 3 0 V Output Voltage VO 0 3 to VDD 3 0 V Power Dissipation PD Ta 25 C 615 mW Operating Temperature TOP 40 to 125 C Storage...

Page 73: ...0 4 V L Output Voltage VOL2 AD7 0 D7 0 IOL2 3 2 mA 0 4 V Output Leakage Current IIH1 PRDY SWAIT AD7 0 D7 0 VI VDD 0 V 1 0 1 0 A Dynamic Supply Current IDD fOSC 16 MHz No Load 9 mA SLEEP Mode 400 A Sta...

Page 74: ...HRA 27 ns PRD H Level Width tWRDH 27 ns PRDY L Delay Time tARLDLY 35 ns PRDY L Level Width tWRDYL 0 2 5T ns Data Output Delay Time from PRDY tARDDLY 35 ns PWR Hold Time from PRDY tARWDLY 10 ns Input D...

Page 75: ...Output Enable Time tCSODLY 30 ns SDO Output Disable Time tCSZDLY 30 ns SDO Output Delay Time tPD 30 ns SRW Setup Time tRS 10 ns SRW Hold Time tRH 0 ns SWAIT Output Delay Time tSRDLY 2T ns SWAIT H Lev...

Page 76: ...0 AD7 0 D7 0 PRD SRW PRDY SWAIT tARDDLY Note The PRDY signal may be output depending on the internal state of the MSM9225B Figure 5 1 Read Access Timing Write access timing tcyc tWAH tWRH tWDS tARLDL...

Page 77: ...tHRA tAS PALE don t care tARDDLY tRS Note The PRDY signal may be output depending on the internal state of the MSM9225B Figure 5 3 Read Access Timing Write access timing tcyc tAH tWRH tARLDLY tWRDYL...

Page 78: ...H tHRA tAS PALE tAH tARDDLY tRS Note The PRDY signal may be output depending on the internal state of the MSM9225B Figure 5 5 Read Access Timing Write access timing tcyc tWRH tARLDLY tWRDYL tWS tWALEH...

Page 79: ...e access timing Note The SWAIT signal will be output during the interval between address and data transfers don t care Figure 5 8 Write Access Timing PRD SRW PRDY SWAIT tWRDY CS tCS tCP tCW tCW tDH tD...

Page 80: ...MSM9225B User s Manual Chapter 5 Electrical Characteristics 5 9 5 2 5 Other Timing tWRSTL RESET tWRSTH tWINTL INT tclkcy CLK XT tclkcy Figure 5 9 Other Timing...

Page 81: ...Appendixes...

Page 82: ...0 41 TYP 5 Rev No Last Revised 4 Nov 28 1996 Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in...

Page 83: ...e 6 M0TMSG6 R W 8 Undefined 000D Message 7 M0TMSG7 R W 8 Undefined 000E CAN control register CANC R W 8 01 000F CAN interrupt control register CANI R W 8 00 0010 Message control register M1MCR R W 8 0...

Page 84: ...input output control register TIOC R W 8 00 0030 Message control register M3MCR R W 8 00 0031 Identifier 0 M3IDR0 R W 8 Undefined 0032 Identifier 1 M3IDR1 R W 8 Undefined 0033 Message 0 Identifier 2...

Page 85: ...e mask register 01 GMSK01 R W 8 00 0050 Message control register M5MCR R W 8 00 0051 Identifier 0 M5IDR0 R W 8 Undefined 0052 Identifier 1 M5IDR1 R W 8 Undefined 0053 Message 0 Identifier 2 M5MSG0 M5I...

Page 86: ...e mask register 11 GMSK11 R W 8 00 0070 Message control register M7MCR R W 8 00 0071 Identifier 0 M7IDR0 R W 8 Undefined 0072 Identifier 1 M7IDR1 R W 8 Undefined 0073 Message 0 Identifier 2 M7MSG0 M7I...

Page 87: ...gister M9MCR R W 8 00 0091 Identifier 0 M9IDR0 R W 8 Undefined 0092 Identifier 1 M9IDR1 R W 8 Undefined 0093 Message 0 Identifier 2 M9MSG0 M9IDR2 R W 8 Undefined 0094 Message 1 Identifier 3 M9MSG1 M9I...

Page 88: ...Receive error counter REC R 8 00 00B0 Message control register M11MCR R W 8 00 00B1 Identifier 0 M11IDR0 R W 8 Undefined 00B2 Identifier 1 M11IDR1 R W 8 Undefined 00B3 Message 0 Identifier 2 M11MSG0 M...

Page 89: ...ed reserved 00CF Not used reserved 00D0 Message control register M13MCR R W 8 00 00D1 Identifier 0 M13IDR0 R W 8 Undefined 00D2 Identifier 1 M13IDR1 R W 8 Undefined 00D3 Message 0 Identifier 2 M13MSG0...

Page 90: ...ed reserved 00EF Not used reserved 00F0 Message control register M15MCR R W 8 00 00F1 Identifier 0 M15IDR0 R W 8 Undefined 00F2 Identifier 1 M15IDR1 R W 8 Undefined 00F3 Message 0 Identifier 2 M15MSG0...

Page 91: ...4th Ver When the MSM9225B is in the bus off state this operation is invalid Even if the above operation is done the error counters are not cleared and the bus off state also is not released was added...

Page 92: ...MSM9225B User s Manual Version 1 0 May 2000 Version 2 0 September 2000 Version 3 0 February 2001 Version 4 0 July 2001 2001 Oki Electric Industry Co Ltd FEUL9225B 04...

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