INSTALLATION GUIDE
18-Slot NI PXIe-1065 Backplane
This guide describes installation requirements for the 18-slot
NI PXIe-1065 backplane.
Contents
NI PXIe-1065 Backplane Overview ....................................................... 2
Interoperability with CompactPCI................................................... 3
System Controller Slot..................................................................... 3
Hybrid Peripheral Slots.................................................................... 4
PXI Peripheral Slots......................................................................... 4
PXI Express Peripheral Slots ........................................................... 4
System Timing Slot ......................................................................... 5
PXI Local Bus.................................................................................. 6
PXI Trigger Bus............................................................................... 7
System Reference Clock .................................................................. 8
PXIe_SYNC_CTRL ........................................................................ 10
Mechanical Requirements....................................................................... 11
Mounting.......................................................................................... 11
Cooling............................................................................................. 11
Handling.................................................................................................. 12
Dimensions ...................................................................................... 12
Electrical Requirements .......................................................................... 13
PXI Connectors................................................................................ 13
Power ............................................................................................... 14
Connector J205 ......................................................................... 14
Connector J206 ......................................................................... 16
Connector J200 ......................................................................... 17
Connectors J213, J214, J215, and J216 .................................... 17
Backplane Specifications ................................................................. 17
System Synchronization Clock (PXI_CLK10, PXIe_CLK100,
PXIe_SYNC100) Specifications................................................... 18
10 MHz System Reference Clock: PXI_CLK10 ...................... 18
100 MHz System Reference Clock: PXIe_CLK100 and
PXIe_SYNC100 .................................................................... 18
External Clock Source .............................................................. 19
