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NAT-MCH Clock-Module – Technical Reference Manual

NAT-MCH
Clock-Module
Technical Reference Manual V 1.4
CLK Module HW
Revision 2.1 and Revision 2.3

Summary of Contents for NAT-MCH

Page 1: ...NAT MCH Clock Module Technical Reference Manual NAT MCH Clock Module Technical Reference Manual V 1 4 CLK Module HW Revision 2 1 and Revision 2 3...

Page 2: ...Reference Manual Version 1 4 N A T GmbH 2 The NAT MCH has been designed by N A T GmbH Kamillenweg 22 D 53757 Sankt Augustin Phone 49 2241 3989 0 Fax 49 2241 3989 10 E Mail support nateurope com Inter...

Page 3: ...r indirect damages including lost profits lost savings delays or interruptions in the flow of business activities including but not limited to special incidental consequential or other similar damages...

Page 4: ...DULE 15 7 BOARD FEATURES 16 8 FUNCTIONAL BLOCKS 18 8 1 STRATUM 3 PLL 18 8 2 MICROPROCESSOR 19 8 3 CLK MULTIPLEX FUNCTION 19 8 4 M LVDS HCSL TRANSCEIVER 19 9 LOCATION OVERVIEW 21 10 CONNECTORS 23 10 1...

Page 5: ...11 3 19 PLL Control 1 Register 45 11 3 20 PLL Control 2 Register 46 11 3 21 PLL Output Signals Register 47 11 3 22 Reserved Register 48 11 3 23 Synchronized Clock Register 49 11 3 24 LED2 Control Regi...

Page 6: ...ister 34 Table 18 SRC_SEL2 Register Bits 34 Table 19 SRC_SEL3 Register 35 Table 20 SRC_SEL3 Register Bits 35 Table 21 SRC_SEL_CLK1_UD Register 36 Table 22 SRC_SEL_CLK1_UD Register Bits 36 Table 23 SRC...

Page 7: ...Register 48 Table 47 RES_3 Register 48 Table 48 RES_4 Register 48 Table 49 RES_5 Register 48 Table 50 RES_6 Register 49 Table 51 SYNC_CLK Register 49 Table 52 SYNC_CLK Register Bits 50 Table 53 LED2_C...

Page 8: ...sing Unit CU Cooling Unit DMA Direct Memory Access E1 2 048 Mbit G 703 Interface FLASH Programmable ROM FRU Field Replaceable Unit J1 1 544 Mbit G 703 Interface Japan K kilo factor 400 in hex factor 1...

Page 9: ...AMC 3 Rev 1 0 PICMG SFP 0 Rev 1 0 System Fabric Plane Format IPMI Specification v2 0 Rev 1 0 Product Safety The board complies with EN60950 and UL1950 PLL Input Frequencies To be sourced from externa...

Page 10: ...eliveries from its suppliers Special attention and care has been paid to the production cycle so that wherever and whenever possible RoHS components are used with N A T hardware products already 2 2 C...

Page 11: ...ndicate that these products within the European Community must not be disposed with regular waste If you have any questions on the policy of N A T regarding the Directive 2002 95 EC of the European Co...

Page 12: ...ixed on to The CLK Module must be completely connected and joint to the Basic PCB before the NAT MCH can be stacked into a MicroTCA backplane as one device For further requirements refer to the requir...

Page 13: ...ing functions can be enabled generation and distribution of synchronized clock signals for up to 12 AMCs reception of clock signals from either of 12 AMCs or from the front panel input and redistribut...

Page 14: ...dant system support of the front panel reference clock In Output Stratum 3 type PLL clock source for telecom applications with various output frequencies Telecom CLK signals can be distributed over al...

Page 15: ...CB Technical Reference Manual Version 1 4 N A T GmbH 15 6 Block Diagram of the NAT MCH CLK Module Figure 2 Block Diagram of the NAT MCH CLK Module backplane connector Connector to Basic PCB Connector...

Page 16: ...Cs or to receive a reference clock signal from any AMC CLK3 The NAT MCH CLK Module implements clock interfaces to 12 AMCs These interfaces can be used to send one of the telecom clock signals or a PCI...

Page 17: ...ic Module via a SPI interface Normal communication between the Microprocessor and the ColdFire is done by IPMI messages via the I C interface The external clock interface on the front panel is connect...

Page 18: ...or from the other NAT MCH CLK1 or CLK3 update can be connected to either of the two reference inputs of the PLL If no reference signal is available the ZL30105 uses a 25 MHz master clock for frequenc...

Page 19: ...k signals is performed by programming a register interface provided by the microcontroller The FPGA for these multiplexers is only assembled with the TC option 8 4 M LVDS HCSL Transceiver The MicroTCA...

Page 20: ...S and SSCH Spread Spectrum Clock HCSL The SSCM option implements M LVDS compliant Transmitter and termination for CLK3 The SSCH option implements HCSL compliant Transmitter and termination Either the...

Page 21: ...rtant components Depending on the chosen options it may be that the board does not include all components named in the location diagram Hardware revision v2 1 implements the SSCM option and v2 3 the S...

Page 22: ...MCH Clock PCB Technical Reference Manual Version 1 4 N A T GmbH 22 Figure 7 Location Diagram of the NAT MCH CLK Module v2 3 top view Figure 8 Location Diagram of the NAT MCH CLK Module v2 3 bottom vi...

Page 23: ...Module are compatible to the other MCH modules all connectors are at the same position Therefore Figure 9 and Figure 10 are guilty for both Hardware revisions Figure 9 Connectors of the NAT MCH CLK Mo...

Page 24: ...61 11 CLK1_Tx CLK1_Rx 160 12 CLK1_Tx CLK1_Rx 159 13 GND GND 158 14 TxFB 1 RxFB 1 157 15 TxFB 1 RxFB 1 156 16 GND GND 155 17 TxFB 2 RxFB 2 154 18 TxFB 2 RxFB 2 153 19 GND GND 152 20 TxFB 3 RxFB 3 151 2...

Page 25: ...K1 1 CLK2 1 121 51 CLK1 1 CLK2 1 120 52 GND GND 119 53 CLK1 2 CLK2 2 118 54 CLK1 2 CLK2 2 117 55 GND GND 116 56 CLK1 3 CLK2 3 115 57 CLK1 3 CLK2 3 114 58 GND GND 113 59 CLK1 4 CLK2 4 112 60 CLK1 4 CLK...

Page 26: ...CLK1 12 CLK2 12 87 85 GND GND 86 10 3Connector Con2 Interface to Basic PCB Connector CON2 connects the NAT MCH CLK Module with the Basic PCB Table 4 Connector to Basic PCB CON2 Pin No Signal Signal P...

Page 27: ...2V 12V 4 5 PCIeCLK_P 3 3V MP 6 7 PCIeCLK_N SPICLK 8 9 GND expansion3 10 11 MOSI MISO 12 13 GND SPISEL_HUB PCB 14 15 SCL nRESET_CLK PCB 16 17 SDA nRESET_HUB PCB 18 19 GND GND 20 10 5Connector JP1 Alter...

Page 28: ...tion interface between the microcontroller and the CPU of the Basic Module All communication is based on IPMI Messages 11 3Register Functions that are controlled by following registers are realized wi...

Page 29: ...0x01 Default value 0xXX Bit 7 6 5 4 3 2 1 0 Access R R R R R R R R Func PCB_REV Bit 7 to 4 contains the major revision and bit 3 to 0 contains the minor revision That means if the PCB revision is e g...

Page 30: ...f the Altera FPGA Table 10 FPGA Revision Register FPGA Revision Address 0x03 Default value of running FPGA revision Bit 7 6 5 4 3 2 1 0 Access R R R R R R R R Func FPGA_REV Bit 7 to 4 contains the maj...

Page 31: ...dress 0x04 Default value 0x00 Bit 7 6 5 4 3 2 1 0 Access R R R R W R W R W R W R W Func REF0_SEL Table 12 REF0_SEL Register Bits Bit Name Function 4 0 REF0_SEL Reference Select for REF0 input of the P...

Page 32: ...dress 0x05 Default value 0x00 Bit 7 6 5 4 3 2 1 0 Access R R R R W R W R W R W R W Func REF1_SEL Table 14 REF1_SEL Register Bits Bit Name Function 4 0 REF1_SEL Reference Select for REF1 input of the P...

Page 33: ...gister Bits Bit Name Function 4 0 SRC_SEL_ CLK1 Selects the output of the PLL which is connected to CLK1 0x01 C19o 0x02 C16o 0x03 C8 C32o 0x04 C4 C65o 0x05 C2o 0x06 C1 5o 0x07 C3o 0x08 C6 8 4 34 44o 0...

Page 34: ...gister Bits Bit Name Function 4 0 SRC_SEL_ CLK2 Selects the output of the PLL which is connected to CLK2 0x01 C19o 0x02 C16o 0x03 C8 C32o 0x04 C4 C65o 0x05 C2o 0x06 C1 5o 0x07 C3o 0x08 C6 8 4 34 44o 0...

Page 35: ...Bits Bit Name Function 4 0 SRC_SEL_ CLK3 Selects the output of the PLL which is connected to CLK3 0x01 C19o 0x02 C16o 0x03 C8 C32o 0x04 C4 C65o 0x05 C2o 0x06 C1 5o 0x07 C3o 0x08 C6 8 4 34 44o 0x09 F1...

Page 36: ...C_SEL_CLK1_UD Register Bits Bit Name Function 4 0 SRC_SEL_ CLK1_UD Selects the output of the PLL which is connected to CLK1 Update 0x01 C19o 0x02 C16o 0x03 C8 C32o 0x04 C4 C65o 0x05 C2o 0x06 C1 5o 0x0...

Page 37: ...C_SEL_CLK3_UD Register Bits Bit Name Function 4 0 SRC_SEL_ CLK3_UD Selects the output of the PLL which is connected to CLK3 Update 0x01 C19o 0x02 C16o 0x03 C8 C32o 0x04 C4 C65o 0x05 C2o 0x06 C1 5o 0x0...

Page 38: ...tting this bit to a logic high enables the transmit function for CLK3 Update 3 2 no function write as 0 and ignore when read 4 nRE_CLK1 Clearing this bit enables global the read function for CLK1 Note...

Page 39: ...high enables the transmit function for CLK1 for AMC Slot 1 1 DE_CLK1 2 Setting this bit to a logic high enables the transmit function for CLK1 for AMC Slot 2 2 DE_CLK1 3 Setting this bit to a logic hi...

Page 40: ...R W R W R W Func DE_CLK1 12 DE_CLK1 11 DE_CLK1 10 DE_CLK1 9 Table 30 TRANSC_CTL3 Register Bits Bit Name Function 0 DE_CLK1 9 Setting this bit to a logic high enables the transmit function for CLK1 for...

Page 41: ...high enables the transmit function for CLK2 for AMC Slot 1 1 DE_CLK2 2 Setting this bit to a logic high enables the transmit function for CLK2 for AMC Slot 2 2 DE_CLK2 3 Setting this bit to a logic hi...

Page 42: ...R W R W R W Func DE_CLK2 12 DE_CLK2 11 DE_CLK2 10 DE_CLK2 9 Table 34 TRANSC_CTL5 Register Bits Bit Name Function 0 DE_CLK2 9 Setting this bit to a logic high enables the transmit function for CLK2 for...

Page 43: ...high enables the transmit function for CLK3 for AMC Slot 1 1 DE_CLK3 2 Setting this bit to a logic high enables the transmit function for CLK3 for AMC Slot 2 2 DE_CLK3 3 Setting this bit to a logic hi...

Page 44: ...W R W R W R W Func DE_CLK3 12 DE_CLK3 11 DE_CLK3 10 DE_CLK3 9 Table 38 TRANSC_CTL7 Register Bits Bit Name Function 0 DE_CLK3 9 Setting this bit to a logic high enables the transmit function for CLK3 f...

Page 45: ...tion 0 PLL_RST Setting this bit to a logic high resets the PLL 2 1 REF_SEL Selects which Reference input is the active reference of the PLL 0b00 REF0 Reference as defined by REF0_SEL Register 0b01 REF...

Page 46: ...t phase 2 SEC_MSTR Clearing this bit selects the Primary Master mode of operation with 1 8 Hz or 3 6 Hz DPLL loop filter bandwidth Setting this bit selects Secondary Master mode which forces the PLL t...

Page 47: ...p Register Bits Bit Name Function 0 REF_FAIL0 A logic high shows that the Reference that is connected to REF0 of the PLL has failed 1 REF_FAIL1 A logic high shows that the Reference that is connected...

Page 48: ...Func Table 46 RES_2 Register Reserved 2 Address 0x16 Default value 0x00 Bit 7 6 5 4 3 2 1 0 Access R W R W R W R W R W R W R W R W Func Table 47 RES_3 Register Reserved 3 Address 0x17 Default value 0x...

Page 49: ...s R W R W R W R W R W R W R W R W Func 11 3 23 Synchronized Clock Register The Synchronized Clock Register contains extended features to choose a source that can be distributed to all AMCs Table 51 SY...

Page 50: ...0x07 C3o 0x08 C6 8 4 34 44o 0x09 F16o 0x0B PLL_REF0 0x0C PLL_REF1 0x0D EXTREF_IN 0x0E TIC_100u 0x0F RES do not use 0x10 RES do not use 0x11 SW_CLK all other values result in no connection Note The out...

Page 51: ...t value 0x00 Bit 7 6 5 4 3 2 1 0 Access R R R R R R W R W R W Func LED2_CTR Table 54 LED2_CTR Register Bits Bit Name Function 2 0 LED2_CTR selects the LED2 function 0b000 LED2 is on if the PLL is lock...

Page 52: ...ion in reset 01 Automatic holdover switch back Switches over to internal generated 10MHz clock if reference fails Switches back to reference if reference is again valid 10 Automatic holdover no switch...

Page 53: ...UTP_CTL Register Bits Bit Name Function 5 0 EXT_REF_O UT_MUX These bits control the EXT_REF_OUT_MUX multiplexer The output of this multiplexer is driven out of the external reference clock connector o...

Page 54: ...refer to Table 4 If enabled the selected signal is driven out via EXTREF_OUT_P Depending on the HIGH AMPL bit either the complementary of the selected signal or a 0 is driven out via EXTREF_OUT_N Sinc...

Page 55: ...NAT MCH Clock PCB Technical Reference Manual Version 1 4 N A T GmbH 55 Known Bugs Restrictions none...

Page 56: ...H Clock PCB Technical Reference Manual Version 1 4 N A T GmbH 56 Appendix A Reference Documentation 1 Zarlink ZL30105 T1 E1 SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTCA and H 110...

Page 57: ...anged SYNC_CLK register description ks 1 2 05 06 2008 12 08 2008 Added description of holdover function and external reference clock interface ks 1 3 02 10 2008 Added description of HCSL and M LVDS di...

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