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Summary of Contents for M68MM01

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Page 2: ...uracies Furthermore such information does not convey to the purchaser of the product described any license under the patent rights of Motorola Inc or others Motorola reserves the right to change specifications without notice EXORciser and EXbug are trademarks of Motorola Inc Fourth Edition Copyright 1979 by Motorola Inc Previous Edition Copyright 1977 All Rights Reserved M68MM01 D4 April 1979 ...

Page 3: ... Diagram Description 3 1 4 MAINTENANCE INFORMATION 4 1 4 1 Introduction 4 1 Figure 1 1 1 2 3 1 3 2 4 1 Table 1 1 2 1 2 2 2 3 2 4 4 1 LIST OF ILLUSTRATIONS Page Monoboard Microcomputer 1 1 2 Monoboard Microcomputer 1 Address Map 1 4 Monoboard Microcomputer 1 Block Diagram 3 3 Monoboard Microcomputer 1 Schematic Diagram 3 5 Monoboard Microcomputer 1 Parts Location 4 3 LIST OF TABLES Page Monoboard M...

Page 4: ...nd control bus drivers to interface Monoboard Microcomputer 1 wilh other modules in the family or with the EXORciser TTL signal level inputs and TTL signal tevel three state or open collector outputs Oplional maling connectors and pullup resistors for PIA oulput lines available on M68MMOH and M68MM01 2 only See schemalic and parts list 1 3 SPECIFICATIONS Monoboard Microcomputer 1 specifications ar...

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Page 6: ...l Micromodules are to be used with Monoboard Microcomputer 1 their address must be selected to fall within the available memory locations 200Q 4FFF and 6000 BFFF Monoboard Microcomputer 1 is also bus compatible with the M6800 EXORciser This versatility provides the user with the means to develop and debug both his hardware and software and to troubleshoot production hardware Thus the user can take...

Page 7: ...800 57FF 5000 I FFF 0 00 AMBIGUOUS ROM ADDRESSES IA 12 AND A 13 ARE DON T CARE PREFERABLE ROM ADDRESSES NOT AVAILABLE All NOT INCLUDED IN MEM NOT SELD MODULE PIA 3 ADORESSES NOT AVAILABLE All NOT INClUDED IN MEM NOT SELD AMBIGUOUS RAM ADDRESSES AIO A II A12 ARE DON T CARE 03F F 0000 MODULE RAM ADDRESSES Figure 1 2 Monoboard Microcomputer 1 Address Map 1 4 ...

Page 8: ... MPU 5Vdc at 1 lA max 12Vdc at OmA 12Vdc at 5mA max 5Vdc at 1 1 A max 12Vdc at 260mA max 12Vdc at 180mA max 8 bits 16 bits 8 16 or 24 bits 72 variable length instructions Seven Addressing Modes Direct Relative Immediate Indexed Extended Implied and Accumulator Crystal controlled 1 MHz with capability to work with dynamic memories 4K bytes of memory sockets only 1K byte of memory 3 MC6820 PIA 48 da...

Page 9: ...le active transition and buffered with inverting driver Peripheral control output buffered with inverting open collector driver Eight data output lines buffered with inverting open collector drivers TTL voltage compatible interrupt input with programmable active transition TTL voltage compatible line programmable to act as an interrupt input or as a peripheral control output Eight TTL voltage comp...

Page 10: ...rrupt input with programmable active transition and buffered with inverting driver CB2 Peripheral control output buffered with inverting open collector driver PBO PB7 Eight TTL voltage compatible data lines that are hardware configured inverting input or output lines These data lines must be programmed to correspond to the optionally installed input or output buffers Line Terminators Optional pull...

Page 11: ...age to the printed circuit board 2 4 INSTALLATION INSTRUCTIONS Since Monoboard Microcomputer 1 is intended for user designed microcomputer based systems no special instatlation instructions are provided However before installing the unit into the user s system or into the EXORciser install the desired EROM or ROM devices into the appropriate sockets and remove all power from the system CAUTION Ins...

Page 12: ...VUA signal must be the same as the VMA signal generated by the MPU Therefore the jumper connections required are shown in note B Kl Kl iif J CROPRoc sseR 1 1 CROPROC sseR MICROMODULE 1 3 I VMA MICROMOOULE 3 VMA VMA I _ I VMA I I i I _ MICRQMODU LE MICRDMDOULE DEBUG 0 EI VUA MICRQMOOULE I 61 VUA VUA L _ _ J VUA L _ __ J MICROPROCESSOR MICROPROCESSO A V A V A NOTE A NOTE B 2 5 2 2 Operating with Ext...

Page 13: ...ING INFORMATION The MPU addresses the PIAsas if they were memory Therefore allcommands to the PI As are executed by the MPU as memory reference instructions The M6800 Microprocessor Applications Manual illustrates the PI A addressing and the operation being performed on the selected PIA register Note that bit 2 of the PIA control register is used to specify either the PIA speripheral interface reg...

Page 14: ...ftware interrupt polling routine to interrogate each of these devices and determine the device initiating the interrupt This polling routine on determining the IRQ initiated device causes the MPU to vector to the appropriate service routine In preparing the interrogation routine you must assign priorities to the devices by assigning their position in the interrogation polling routine The device in...

Page 15: ... non maskable interrupt be generated within the machine The MPU will wait until it completes the instruction being executed before it recognizes the NMI Signal At that time the MPU will begin its non maskable interrupt sequence F VMA VALID MEMORY ADDRESS Thisoutput is available jumper selected when Monoboard Microcomputer 1 is used with the EXORciser Debug Module to indicate that there is a valid ...

Page 16: ... go to their off high impedance state and other outputs to their normally inactive state A maskable interrupt or non maskable interrupt removes the MPU from the Wait state Not Used 12 Vdc Used by the Erasable Read Only Memories EROM s Not Used Not Used DATA bus bit 3 This bi directionalline when enabled provides a two way data transfer between Monoboard Microcomputer 1 and any other plug in module...

Page 17: ...d of an instruction Bus Available will be at a high level Valid Memory Address will be at a low level and all other three state lines will be in their off or high impedance state T he Halt line must go low with the leading edge of the phase one clock cJ 1 to insu re single instruction operation lithe Halt line does not go low with the leading edge of the phase one clock one or two instructi on ope...

Page 18: ...r use wi th the Debug Module VUA is supplied as an input by the Debug Module 11 12 VDC 12 Vdc Same as 12 Vdc on P1 M 12 REFREQ REFRESH REQUEST This input signal when low initiates a memory refresh cycle of the dynamic memory modules During the refresh operation the clock circu it is inhibited from generating its 1and 2 MPU clock signals but still generates the MEMCLK signal 13 REF GRANT REFRESH GR...

Page 19: ...S bus bit 12 Same as A140n P1 M 35 A11 ADDRESS bus biI11 Same as A140n P1 M 36 A8 ADDRESS bus bit 8 Same asA140n P1 M 37 A7 ADDRESS bus bit 7 Same asA140n P1 M 38 A4 ADDRESS bus bit 6 Same as A140n P1 M 39 A3 ADDRESS bus bit 3 Same as A140n P1 M 40 AO ADDRESS bus bitO Same as A14 on P1 M 41 42 43 COM COMMON aroundl 2 10 ...

Page 20: ...pin 1except bit 1of the A data direction register controls this line GROUND Signal return line PERIPHERAL data line Section 1 bit 2 PIA1 Same as PAO 1 on pin 1 except bit 2 of the A data direction register controls this line GROUND Signal return line PERIPHERAL data line Section A bit 3 PIA1 Same as PAO 1 on pin 1 except bit 3 of the A data direction register controls this line GROUND Signal retur...

Page 21: ... bit 0 of the Bdata direction register causes this line to function as an output 18 GND GROUND Signal return line 19 PB1 1 PERIPHERAL data line Section B bit 1 PIA1 Same as PBO l on pin 17 except bit 1 of the B data direction register controls this line 20 GND GROUND Signal return line 21 PB2 1 PER IPHERAL data line Section B bit 2 PIA1 Same as PBO l on pin 17 except bi t 2 of the B data direction...

Page 22: ... pin 17 except bit 7of the B data direction register controls this line GND GROUND Signal return line PAO 2 PERIPHERAL data line Section A bit 0 PI A2 This peripheral data line in Section A of PIA2 U21 can be pro grammed to act either as an input line or as an output line A 0 in bit 0 of the A data direction reg ister causes th is line to function as an input and a 1 causes this line to function a...

Page 23: ...ontrol register 4 GND GROUND Signal return line 5 CB2 1 Peripheral CONTROL line line CB2 PIA1 Negative true buffered output This peripheral control line of PIA1 U20 must be programmed to operate as a peripheral control output line The function of this line is program controlled by the B control register 6 GND GROUND Signal return line 7 CA1 2 Peripheral CONTROL line line CA1 PIA2 This peripheral c...

Page 24: ...ets the interrupt flag of the B control register The active transi tion of the signal is program controlled by the B control register 14 GND GROUND Signal return line 15 CA1 3 Peripheral CONTROL line line CA1 PIA3 Negative true buffered input This peripheral control line on PIA3 U22 is an input line that sets the interrupt flag of the A control reg ister The active transition of the signal is prog...

Page 25: ...9 CB1 3 Peripheral CONTROL line line CB1 PIA3 Negative true buffered input This peripheral control line of PIA3 U22 is an input line that sets the interrupt flag of the B control register The active transition of the signal is program controlled by the B control register 20 GND GROUND Signal return line 2 17 ...

Page 26: ...ame as PBO 2 on pin 1 except bit 2 of the B data direction register controls this line 6 GND GROUND Signal return line 7 PB3 2 PERIPHERAL data line section B bit3 PIA2 Same as PBO 30n pin 1 except bit 3 of the B data direction register controls this line 8 GND GROUND Signal return line 9 PB4 2 PERIPHERAL data line section B bit 4 PIA2 Negative True Buffered Input Output This peripheral data line i...

Page 27: ... the B data direction register controls this line 16 GND GROUND Signal return line 17 PAO 3 PERI PHERAL data line section A bit 0 PIA3 This peripheral data line in section A of PIA3 U22 can be pro grammed to act eitheras an input line or as an output line A 0 in bit 0 of the A data direction registerc8uses this line to function as an input and a 1 causes this line to function as an output 18 GND G...

Page 28: ...ROUND Signal return line 29 PA6 3 PERI PHERAL data line section A bit 6 PIA3 Same as PAO 3 on pin 17 except bil6 of Ihe A data direction register controls this line 30 GND GROUND Signal return line 31 PA7 3 PERIPHERAL data line secti on A bit 7 PIA3 Same as PAO 3 on pin 17 except bit 7 of the A data direction register controls this line 32 GND GROUND Signal return line 33 PBO 3 PERIPHERAL data lin...

Page 29: ...ls this line 38 GND GROUND Signal return line 39 PB3 3 PERIPHERAL data line section B bit 3 PIA3 Same as PBO 3 on pin 33 except bit 3 in the B data direction register con trols this line 40 GND GROUND Signal return line 41 PB4 3 PERIPHERAL data line secti on B bit 4 PIA3 Same as PBO 3 on pin 33 except bit 4 in the B data direction register con trols this line 42 GND GROUND Signal return line 43 PB...

Page 30: ...t bit 7 in the B data direction reg ister controls this line 48 GND GROUND Signal return line 49 CB2 3 Peripheral CONTROL line line CB2 PIA3 Negative True Buffered Output This peripheral control line of PIA3 U22 must be programmed to operate as a peripheral control outpul line The function of this line is program controlled by the 8 control register 50 GND GROUND Signal return line 2 22 ...

Page 31: ...used within the system Since Monoboard Microcomputer 1 incorporates only static type RAM devices this refresh capability is not required However for any dynamic RAM module that might be used this capability has been included To initiate a refresh operation the requesting module places a low level RR Refresh Request command on the Micromodule control bus When the clock circuit produces the next MEM...

Page 32: ...ns addressed by the MPU may be located either on or off the Monoboard Microcomputer 1 depending upon the application The address decoder uses a non fully decoded address decoding scheme to uniquely address each ER OM ROM RAM or PIA located on Monoboard Microcomputer 1 The address map shown in Figure 1 2 is a resu lt of this decoding scheme If the MPU generates an address for a memory location othe...

Page 33: ... AIW Jo2TTL GO HALT GO HALT MEM NOT SELD NMI CONTROL NMi I BUS MPU 1 lAO INTERFACE iRQ RESET I I I I i VMA VMA I r I VMA Kl w 1 9 D e VUA VMA e 0 l i L __ W N D MEM NOT SELO e I 002 TTL 2TTL MEM eLK MEM eLK CLOCK I RR AA HOLD 1 I REFRESH I MEM CONTROL eLK FLIP FLOP AO RESTART RESET RESET CIRCUIT 3 3 ...

Page 34: ... I T I C A J t l CO iC UR ATtO 1 S 0 0 l 4 0O 0 UBU W TI OUT E U 3 5 L L Figure 3 2 Monoboard Microcomputer 1 Schematic Diagram ...

Page 35: ... ij IU I 1 r 140_ 1 J _ _ 9 __ t r II to f I fj I Iii 1 0 1 0 T 0 _ _ _ _ _ _ _ ____ _0 _ _ _ __ __ _ _ _ 3 6 SClo MAT 1C MICP O MODVI E I ICRO COMPUf R I I ...

Page 36: ...t 1 Ur f to u II f OM f 1 iIlO t _a_ i I h If W J e r 0 t n M tIC 1 u loWr I J y r ___ 14 I uy I l 1 4 13 12 U J I rI l1J F FIGURE I FIGURE 2 JD C RESISTOR NCTWORKS ARE CUSTOMER OPTIONS QE STOR FAC CONFICoUPAT ONS M 8E loS IN EI THER FIGURE lOR 2 O i CO T O _ t ___ _ I 3 7 ...

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Page 38: ... Alternate Capacitor Ceramic AD l F 50 Vdc 20 C5 C36 21NW9702A09 Capacitor Ceramic O l F 50Vdc AD Kl K3 28NW9802B88 Header Post Double Row 6 pin AD K2 28NW9802B22 Header Post Double Row 10 pin AD Rl 17NW9625A06 Resistor Fixed Wirewound AD 4 3 ohms 10 R2 Rll 06SW 124B22 Resistor Fixed Carbon 1 0 Megohm AD 5 1 4W R3 R9 06SW 124AOl Resistor Fixed Carbon 10 ohms AD 5 1 4W R4 R8 R12 06SW 124A65 Resisto...

Page 39: ... Profile AD 14 pin used with U23 U30 U31 U33 4 required U24 51NW9615C69 I C SN74LS138N AD U26 U29 U32 51NW9626A13 Resistor Network 4 7 kO 15 per AD package for M68MMOH only 51 NW9626A20 Resistor Network 220 ohms 330 ohms AD 14 per package for M68MMOl 2 only 09NW981 1A04 Socket IC Dual Inline Low Profile AD 16 pin used with U26 U29 U32 3 required U34 U41 51NW9615D35 I C 2102AN RAM AD U42 51NW9626A0...

Page 40: ... 0ii oO0O 000 1 1 I 1 aDU1B QU19 0 U20 U21 I U22 ABO 3 1 lu oD 0I II I I31 1 0 U11 A2 U12 U13 U14 U1S U16 U17 31 1 0 BOD 31 1 0 110 31 1 U1 us P1 DA1 o CJ K1 A9 Figure 4 1 Monoboard Microcomputer 1 Parts Location U10 K2 o ...

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