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Technical Data
Advance Information
MSC8101/D
Rev. 6, 11/2002
Networking Digital
Signal Processor
(mask set 2K42A)
Figure 1. MSC8101 Block Diagram
UTOPIA
Other
Peripherals
MII
TDMs
CPM
M
CC / UA
RT
/ HDL
C /
T
ra
n
s
p
a
re
n
t
/
E
ther
net /
F
a
s
t E
ther
net
/ A
T
M / S
C
C
PIT
System Protection
Reset Control
Clock Control
SIU
8/16-bit
Host
SC140
Power
Management
Clock/PLL
64-bit XA Data Bus
128-bit P-Bus
64-bit XB Data Bus
Extended Core
Interface
64-bit Local Bus
64-bit System Bus
Core
•
•
•
S
e
ri
al
Inter
fac
e and
T
S
A
3
×
FCC
4
×
SCC
SPI
I2C
2
×
MCC
2
×
SMC
Interrupt
Timers
Baud Rate
Parallel I/O
Generators
Controller
Dual Ported
RAM
Program
Sequencer
Address
Register
File
Data ALU
Register
File
Address
ALU
Data
ALU
64/32-bit
System
Bus
Interrupts
EOnCE™
JTAG
2
×
SDMA
RISC
Interface
DMA
Engine
Bridge
Q2PPC
Bridge
Boot
ROM
SRAM
512 KB
128-bit QBus
MEMC
L1 Interface
HDI16
MEMC
{
PIC
EFCOP
SIC_EXT
SIC
Interrupts
The Motorola
MSC8101 16-bit
Digital Signal
Processor (DSP) is the
first member of the
family of DSPs based
on the StarCore™
SC140 DSP core. The
MSC8101 is offered in
three core speed levels:
250, 275, and 300 MHz.
The Motorola MSC8101 DSP is a very versatile
device that integrates the high-performance SC140
four-ALU (Arithmetic Logic Unit) DSP core along
with 512 KB of on-chip memory, a
Communications Processor Module (CPM), a
64-bit bus, a very flexible System Integration Unit
(SIU), and a 16-channel DMA engine on a single
device. With its four-ALU core, the MSC8101 can
execute up to four multiply-accumulate (MAC)
operations in a single clock cycle. The MSC8101
CPM is a 32-bit RISC-based communications
protocol engine that can network to Time-Division
Multiplexed (TDM) highways, Ethernet, and
Asynchronous Transfer mode (ATM) backbones.
The MSC8101 60x-compatible bus interface
facilitates its connection to multi-master system
architectures. The very large on-chip memory, 512
KB, reduces the need for off-chip program and
data memories. The MSC8101 offers 1500 DSP
MMACS (1200 core and 300 EFCOP) or 3600
RISC MIPS performance using an internal 300
MHz clock with a 1.6 V core and independent
3.3 V input/output (I/O). MSC8101 power
dissipation is estimated at less than 0.6 W. Figure
1 shows a block diagram of the MSC8101
processor.
Note: This document contains information on a new product. Specifications and information herein are subject to change without notice.