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MIPI D-PHY Bandwidth Matrix Table

User Guide

FPGA-UG-02041 Version 1.1

May 2018

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Summary of Contents for MIPI D-PHY

Page 1: ...MIPI D PHY Bandwidth Matrix Table User Guide FPGA UG 02041 Version 1 1 May 2018...

Page 2: ...dwidth and Data Rate 15 5 1 Bandwidth and Data Rate Calculation 15 5 1 1 Pixel Clock 15 5 1 2 Total Data Rate or Bandwidth 15 5 1 3 Data Rate per Lane 15 5 1 4 Bit Clock 15 5 2 Examples 15 5 2 1 Examp...

Page 3: ...Implementation 10 Figure 3 3 Unidirectional Transmit HS Mode and Bidirectional LP Mode Interface Implementation 11 Figure 3 4 Unidirectional Transmit HS Mode Only Implementation 12 Figure 4 1 An Examp...

Page 4: ...tive holders The specifications and information herein are subject to change without notice 4 FPGA UG 02041 1 1 Acronyms in This Document A list of acronyms used in this document Acronym Definition CS...

Page 5: ...oosing an FPGA device with the right number of data lanes supporting the required data transfer rate This document describes in details the methods of calculating the bandwidth and data rate of the im...

Page 6: ...Each still image is composed of individual lines of pixel data Figure 2 1 illustrates a conceptual interlaced video frame The progressive video frame is similar to it except for only one field per fr...

Page 7: ...er rate in the later sections of the document 2 1 Video Resolution and Pixel Clock The video resolution is quoted as Width x Height with the unit in pixels for example 1920x1080 means the horizontal w...

Page 8: ...1680 831 59 81 83 5 WXGA 1440x900p 60 Hz 1440 900 1904 934 59 887 106 5 HD 1366x768p 60 Hz 1366 768 1792 798 59 79 85 5 HD 1600x900p 60 Hz RB 1600 900 1800 1000 60 108 WUXGA 1920x1200p 60 Hz RB 1920 1...

Page 9: ...hows the block diagram of the Unidirectional Receiver HS Mode Only interface Figure 3 3 shows the block diagram of the Unidirectional Transmit HS Mode and Bidirectional LP Mode interface Figure 3 4 sh...

Page 10: ...es are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice 10 FPGA UG 02041 1 1 MIPI DPHY TX Device LATTICE F...

Page 11: ...rks of their respective holders The specifications and information herein are subject to change without notice FPGA UG 02041 1 1 11 Lattice FPGA 50 LVDS25E LVCMOS12 LVCMOS12 CLOCK_P CLOCK_N DATA3_P DA...

Page 12: ...registered trademarks of their respective holders The specifications and information herein are subject to change without notice 12 FPGA UG 02041 1 1 Lattice FPGA 70 LVDS25E CLOCK_P CLOCK_N DATA_P DA...

Page 13: ...data format FS P1 P2 FE P4 LSBs P3 P637 P638 P640 LSBs P639 P1 P2 P4 LSBs P3 P637 P638 P640 LSBs P639 P1 P2 P4 LSBs P3 P637 P638 P640 LSBs P639 P1 P2 P4 LSBs P3 P637 P638 P640 LSBs P639 P1 P2 P4 LSBs...

Page 14: ...are single lane configurations Table 4 1 CSI 2 Packet Size Constraints Data Format Odd Even Lines Pixels Bytes Bits YUV420 8 bit Odd 2 2 16 Even 2 4 32 YUV420 10 bit Odd 4 5 40 Even 4 10 80 YUV422 8 b...

Page 15: ...nclude blanking period The Refresh Rate may be referred to as Frame Rate or Vertical Frequency 5 1 2 Total Data Rate or Bandwidth The bandwidth of a given video format is simply a product of the Pixel...

Page 16: ...ferential termination Dedicated MIPI D PHY inputs buffer Internal 100 differential termination LP Mode LVCMOS12 VCCIO 1 2 V LVCMOS12 VCCIO 1 2 V LVCMOS12 VCCIO 1 2 V Dedicated MIPI D_PHY input buffer...

Page 17: ...X4 X8 and ODDRX2 X4 X8with data and clock centered aligned See the MIPI Data Rate Calculation section for the calculations based on current data sheet Re calculate to confirm these values with the mos...

Page 18: ...of calculating the windows if higher data rate is desired The window for higher data rate does meet MIPI Alliance Specification but can still be practical in the user s implementation Check the lates...

Page 19: ...2 Inputs with Clock and Data 10 Bits Wide Centered at Pin GDDRX2_RX ECLK Centered Using PCLK Pin for Clock Input tSUGDDR tHOGDDR Data Hold After CLK f MAX_GDDR DDRX2 Clock Frequency 321 405 321 403 32...

Page 20: ...or ECP5 ECP 5G Max 0 321 0 321 0 15 x UI UI 0 321 0 15 2 14 ns Max Data Rate 1 UI 1 2 14 467 Mbps at 0 15 UI Setup Time Hold Time 0 321 0 321 ECP5 ECP5 5G Data Sheet Rev 1 9 at 800 Mbps Generic DDRX2...

Page 21: ...ion can be used tSU tHD Window max tSU tHD 1 Data Rate For 800 Mbps 1 Data Rate 1 25 ns The maximum data rate each device can support on the receiver is limited to the data rate supported with IDDRX2...

Page 22: ...XO2 MachXO3L 0 206 0 15 x UI UI 0 206 0 15 1 373 ns Max Data Rate 1 UI 1 1 373 728 Mbps at 0 15 UI Setup Time Hold Time 0 455 0 455 At 756 Mbps UI 0 661 Tskew 0 661 0 445 0 206 MachXO2 Data Sheet Rev...

Page 23: ...MIPI compliance data rate calculation for LatticeECP3 0 215 0 15 x UI UI 0 215 0 15 1 433 ns Max Data Rate 1 UI 1 1 433 698 Mbps at 0 15 UI Setup Time Hold Time 0 285 0 285 At 1000 Mbps UI 0 5 Tskew 0...

Page 24: ...put Valid Before CLK Output tHD_GDDRX2_centered fDATA_GDDRX2_centered GDDRX2 Data Rate fMAX_GDDRX2_centered GDDRX2 CLK Frequency ECLK 0 442 800 400 0 442 0 56 700 350 0 56 0 676 624 312 0 676 Mb s MHz...

Page 25: ...terface Lane Number and Line Rate Selection Example Matrix Table MachXO2 and MachXO3L 523 Mbps for RX and 728 Mbps for TX I O LatticeECP3 467 Mbps for RX and 698 Mbps for TX I O ECP5 ECP5 5G 467 Mbps...

Page 26: ...185 6 4 371 185 6 4 371 185 6 16 2376 4 594 297 18 2673 24 3564 120 297 8 2376 4 594 297 10 2970 4 742 5 371 16 4752 18 5346 24 7128 UHD 3840x2160p 4400x2250 30 297 8 2376 4 5941 297 4 5941 297 4 5941...

Page 27: ...nce submit a technical support case at www latticesemi com techsupport Revision History Date Version Change Summary May 2018 1 1 Changed document number from UG110 to FPGA UG 02041 Updated document te...

Page 28: ...7th Floor 111 SW 5th Avenue Portland OR 97204 USA T 503 268 8000 www latticesemi com...

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