JYTEK PCIe-5211 User Manual Download

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User Manual Version:

Revision Date:

V1.6.2

Oct . 09

2021

PCIe/PXIe-5211

Counter/Timer Module

User Manual

Summary of Contents for PCIe-5211

Page 1: ...User Manual Version Revision Date V1 6 2 Oct 09 2021 PCIe PXIe 5211 Counter Timer Module User Manual...

Page 2: ...Hardware Driver 12 3 5 Install the SeeSharpTools from JYTEK 12 3 6 Running C Programs in Linux 12 4 Operating PCIe PXIe 5211 14 4 1 Quick Start 14 4 2 Digital I O Operations 14 4 3 Counter Measuremen...

Page 3: ...ing In Finite Mode 20 Figure 12 Edge Counting In Continuous Mode 21 Figure 13 Edge Counting With Implicit Clock 21 Figure 14 Pulse Measurement in Single Mode 22 Figure 15 Pulse Measurement with Explic...

Page 4: ...Two Pulse Encoder with Implicit Sample Clock 47 Figure 44 Two Pulse Encoder In Single Mode 48 Figure 45 Two Pulse Encoder In Continuous Mode 49 Figure 46 Pulse Output in Single Mode 50 Figure 47 Pulse...

Page 5: ...PCI Express bus and multi core optimized drivers and application software to provide high performance capabilities Please check with JYTEK website for the latest 5211 series offering 1 2 Main Feature...

Page 6: ...obtain information from JYTEK Figure 1 JYPEDIA Information In a Learn by Example section the sample program is in bold style such as Counter Input Winform CI Single Edge Counting the property name in...

Page 7: ...has the counter output capability If you do not have a signal source you can use the outputs of PCIe PXIe 5211 as the signal source In this case you need first run example program Counter Output Winf...

Page 8: ...agram The system block diagram of PCIe PXIe 5211 series is shown in Figure 2 It is mainly composed of one DIO module and eight Counter Timer modules providing digital input digital output counter inpu...

Page 9: ...PCIe PXIe 5211 jytek com 5 2 2 Digital IO Specifications Table 1 Digital IO Specifications...

Page 10: ...PCIe PXIe 5211 jytek com 6 2 3 Counter Timer Specifications Table 2 Counter Timer Specifications...

Page 11: ...PCIe PXIe 5211 jytek com 7 2 4 Other Specifications Table 3 Other Specifications...

Page 12: ...PCIe PXIe 5211 jytek com 8 2 5 Front Panel and Pin Definition Figure 3 Front Pannel...

Page 13: ...PCIe PXIe 5211 jytek com 9 Table 4 Pin Defination...

Page 14: ...11 jytek com 10 2 6 Default Routing for Counter Input Output Signals All counter input and output terminals are routed to a certain PFI by default as shown in Table 5 Table 5 Counter Input Output Defa...

Page 15: ...11 in the Window environment you need to install the following software from Microsoft website Microsoft Visual Studio Version 2015 or above NET Framework version is 4 0 or above NET Framework is comi...

Page 16: ...hods properties and enumerations in the object oriented programming environment Once you get yourself familiar with how one JYTEK DAQ module works you should be able to know how to use all other DAQ h...

Page 17: ...PCIe PXIe 5211 jytek com 13 maintain the cross platform compatibility between Windows and Linux using MonoDevelop...

Page 18: ...software and the SeeSharpTools you are ready to use Microsoft Visual Studio C to operate the PCIe PXIe 5211 products If you are already familiar with Microsoft Visual Studio C the quickest way to use...

Page 19: ...escribed below Edge Counting Pulse Measurement Frequency Measurement Period Measurement Two Edge Separation Quadrature Encoder x1 x2 x4 Two Pulse Encoder For buffered acquisition each counter has a se...

Page 20: ...set JY5211CITask Mode to CIMode Single 2 Finite Continuous Mode with Explicit Sample Clock The counting value is stored into the buffer on each rising edge of the sample clock as shown in Figure 6 Fig...

Page 21: ...imple Edge Counting with Implicit Sample Clock To configure the counter to work in this mode set JY5211CITask Mode to CIMode Finite or CIMode Continuous and set JY5211CITask SampleClock Source to CISa...

Page 22: ...direction the counter counts up when the signal is high and counts down when the signal is low as shown in Figure 9 Figure 9 Count Direction To cofigure the count direction use the properties as below...

Page 23: ...Ie 5211 counter0 s edge counting source CTR0_Source Pin 65 negative terminal to the ground GND Pin 66 as shown in Table 2 15 Pin Defination CTR0_Source GND consists of an edge counting counter input S...

Page 24: ...he following numbers as shown Figure 11 Edge Counting In Finite Mode The table in the sample program is a connection diagram for your convenience Direction is set by Direction There are three sample c...

Page 25: ...Mode The numbers are stored in a buffer Counts Change the Sample Clock Source to Implicit Figure 13 Edge Counting With Implicit Clock The numbers are stored in a buffer Counts The counter values are d...

Page 26: ...g value of the duration of the high level or low level is written to the register on each rising or falling edge of the pulse to measure as shown in Figure 14 Figure 14 Pulse Measurement in Single Mod...

Page 27: ...e as the implicit sample clock edge The counting value of the duration of the high level or low level is stored into the buffer on each rising edge of the measured pulse as shown in Figure 16 Figure 1...

Page 28: ...l Learn by Examples 4 3 2 Connect the signal source s positive terminal Ch1 to PCIe PXIe 5211 counter0 s pulse measure source CTR0_Gate Pin 31 negative terminal to the ground GND Pin 32 as shown in Ta...

Page 29: ...vel Duration s Figure 18 Pulse Measure Value In Single Mode The numbers show the duration of High Low Level in one signal period and match the duty cycle set before Finite Continuous Mode Change the f...

Page 30: ...Pulse Measure In Finite Mode The table in the sample program is a connection diagram for your convenience Click Start to begin the finite continuous pulse measurement The result is shown below Figure...

Page 31: ...m 27 The numbers show the duration of High Low Level in one signal period and match the duty cycle set before Please refer to Learn by Examples 4 3 1 Finite Continuous Mode about the difference betwee...

Page 32: ...driver will automatically calculate the frequency according to the HighTick LowTick values and known frequency of the timebase according to the fomular and return the signal frequency to the user 1 To...

Page 33: ...lock Source to CISampleClockSource Internal or CISampleClockSource External 3 Finite Continuous Mode with Implicit Sample Clock Frequency Measurement with implicit sample clock is actually using Pulse...

Page 34: ...sure input terminal JY5211CITask FrequencyMeas Timebase External Terminal External timebase input terminal Learn by Examples 4 3 3 Connect the signal source s positive terminal Ch1 to PCIe PXIe 5211 c...

Page 35: ...de Open Counter Input Winform CI Finite Continuous Frequency Figure 23 Frequency Measure In Finite Mode The table in the sample program is a connection diagram for your convenience Please refer to Lea...

Page 36: ...PCIe PXIe 5211 jytek com 32 Figure 24 Frequency Measure Values In Single Mode...

Page 37: ...rce s positive terminal Ch1 to PCIe PXIe 5211 counter0 s period measure source CTR0_Gate Pin 31 negative terminal to the ground GND Pin 32 as shown in Table 2 15 Pin Defination CTR0_Gate GND consists...

Page 38: ...rm CI Finite Continuous Period and click Start The result is shown below by Period s Figure 26 Period Measure In Finite Mode The table in the sample program is a connection diagram for your convenienc...

Page 39: ...nd the rising edge of the scecond signal is written to the register on each rising edge of the second signal The number of rising edges of timebase between previous rising edge of the second signal an...

Page 40: ...ource to CISampleClockSource Internal or CISampleClockSource External 3 Finite Continuous Mode with Implicit Sample Clock In implicit mode the signal active edge as the implicit sample clock edge The...

Page 41: ...gnal to measure input terminal JY5211CITask TwoEdgeSeparation SecondInputTerminal First signal to measure input terminal JY5211CITask TwoEdgeSeparation Timebase External Terminal External timebase inp...

Page 42: ...ond Signal First Separation s and Second Separation s are different Finite Continuous Mode Open Counter Input Winform CI Finite Continuous Two Edge Separation and click Start The result is shown below...

Page 43: ...ek com 39 Figure 32 Two Edge Separation Measure In Continuous Mode The table in the sample program is a connection diagram for your convenience The result in this picture is similar to the result in S...

Page 44: ...can connect Z signal to it or you can disable Z with property ZReloadEnabled Encoding Type 1 x1 Encoding When A signal leads B signal the counter increases the count value on the rising edge of A sign...

Page 45: ...Quadrature Encoder x4 mode Channel Z Behavior The reload phase is when Z signal is high and A signal and B signal are low Timing Take Encoding x1 mode as an example 1 Single Mode The count value is w...

Page 46: ...ClockSource External 3 Finite Continuous Mode with Implicit Sample Clock In implicit mode the signal active edge as the implicit sample clock edge The count value is stored into the buffer on the tran...

Page 47: ...rst signal input A Pin 65 and second signal input B Pin 63 two negative terminals to the ground GND Pin 32 and GND Pin 28 Set the signal source Ch1 s to squarewave signal f 5Hz Phase 0 and Ch2 s outpu...

Page 48: ...44 Finite Continuous Mode Open Counter Input Winform CI Single Quadrature Encoder and click Start The result is shown below by Count Figure 39 Quadrature Encoder In Finite Mode Figure 40 Quadrature En...

Page 49: ...in the sample program is a connection diagram for your convenience Encoding Type is set by Encode Type x1 x2 x4 When the encode type is changed from x1 to x2 and x4 you can see the rising speed of Cou...

Page 50: ...CITask Type to CIType TwoPulseEncoder to use this function Timing 1 Single Mode The count value is written to the register on each rising edge of the A signal and B signel as shown in Figure 41 Figure...

Page 51: ...d set JY5211CITask SampleClock Source to CISampleClockSource Internal or CISampleClockSource External 3 Finite Continuous Mode with Implicit Sample Clock In implicit mode the signal active edge as the...

Page 52: ...al Signal A input terminal JY5211CITask TwoPulseEncoder BInputTerminal Signal B input terminal Learn by Examples 4 3 7 Connect the signal source s two positive terminals Ch1 Ch2 to PCIe PXle 5211 firs...

Page 53: ...g of the Count Finite Continuous Mode Open Counter Input Winform CI Continuous Two Pulse Encoder and set the numbers as shown Figure 45 Two Pulse Encoder In Continuous Mode The table in the sample pro...

Page 54: ...generation Timing 1 Single Mode 5211 can output a single pulse with a specified pulse configuration The timing diagram of the pulse output is shown in Figure 46 Figure 46 Pulse Output in Single Mode...

Page 55: ...d the currently configured pulses the counter will automatically read the configuration of the next set of pulses to be sent from the buffer and start output The timing diagram is shown in Figure 48 F...

Page 56: ...refer to chapter 4 5 3 for more information about timebase Terminals To change the terminal of signals instead of using its default value as shown in chapter 2 6 using following properties JY5211COTa...

Page 57: ...jytek com 53 Finite Mode Open Counter Output Winform CO Finite and click Start and set the numbers as follow Figure 50 CO In Finite Mode The table in the sample program is a connection diagram for yo...

Page 58: ...Onboard 10MHz Clock Using the on board 10MHz TXCO as the PLL input source can help improve the PLL output clock performance including improving clock accuracy temperature stability and phase noise 2 P...

Page 59: ...counter tasks are running Clock configuration is applied to all tasks including DI DO CI CO The PCIe PXIe 5211 module must be powered off and restarted if the user submits the incorrect clock frequenc...

Page 60: ...driver will be set with the safest value Implicit Using an implicit sampling clock means the counter will send data to the buffer whenever there is a new measurement or count value To use the implici...

Page 61: ...t start until a software trigger is received Digital An external digital trigger is generated when the external trigger source terminal detects a rising edge as shown in Figure 52 Figure 52 Rising Edg...

Page 62: ...every module to start the acquisition task in the same time therefore we could take advange of PXI system which can provide a synchronization pulse PXIe_SYNC100 to coordinate with the acquisition tas...

Page 63: ...you need to wait for the trigger signal to arrive all the tasks will start to work synchronously on a rising edge of the PXIe_SYNC100 signal 4 9 System Synchronization Interface SSI for PCIe Modules T...

Page 64: ...ng the DIP switch which is used to identify the module with different slot positions For example if you want to set the card number to 3 you could turn the position 2 and 1 of the DIP switch to the ON...

Page 65: ...ons Among them are C etc This chapter explains how you can use PCIe PXIe 5211 DAQ card using one of this software 5 1 C JYTEK internaly uses our C drivers to design the C drivers We recommend our cust...

Page 66: ...independently owned and operated franchise It shares JYTEK s philosophy and business approach Together JYTEK entities promote the JYTEK brand technology and products 6 3 JYTEK Hardware Products Accord...

Page 67: ...tware tools Our platform software is also open sourced and is free thus lowering the cost of tests for our customers We are the only domestic vendor to offer complete commercial software and hardware...

Page 68: ...pose or non infringement of intellectual property rights unless such disclaimer is legally invalid JYTEK is not responsible for any incidental or consequential damages related to performance or use of...

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