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HP 3000 SERIES II, System Service Manual

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Page 1: ...PUTER SYSTEM SYSTEM SERVICE MANUAL o l1t Manual Part No 30000 90018 Microfiche Part No 30000 90032 Printed in U S A 8 76 Updates through 2 incorporated 2 77 Update 3 3 77 HEWLETT PACKARD 5303 STEVENS CREEK BLVD SANTA CLARA CALIFORNIA 95050 J ...

Page 2: ...ICULAR PURPOSE Hewlett Packard shall not be liable for errors contained herein or for incidental or consequential damage in connection with the furnishing perfor mance or use of this material This document contains proprietary information which is protected by copyright All rights are reserved No part of this document may be photocopied or reproduced without the prior written consent of Hewlett Pa...

Page 3: ...ii Mar 1977 viii Aug 1977 ix and x Jan 1977 1 1 Dec 1976 1 2 Mar 1977 1 3 to 1 5 Jan 1977 1 6 to 1 27 Aug 1976 1 28 and 1 29 Jan 1977 1 30 Mar 1977 2 1 to 2 21 Dec 1976 Blank Dec 1976 3 1 and 3 2 Dec 1976 3 3 to 3 24 Aug 1976 4 1 Jan 1977 4 2 Aug 1976 4 3 and 4 4 Jan 1977 iii 4 5 to 4 17 Aug 1976 4 18 and 4 19 Dec 1976 4 20 to 4 22 Aug 1976 4 23 Dec 1976 4 24 to 4 32 Aug 1976 4 33 Dec 1976 4 34 Ja...

Page 4: ...e edition change First Edition June 1976 Second Edition Aug 1976 Update 1 Dec 1976 Update 2 Jan 1977 Update 3 Mar 1977 iv Revised and reprinted in Aug 1976 to incorporate infor mation concerning Fault Correcting Memory Appendix A IC Logic Symbology has been removed from this manual and will appear in the Engineering Diagrams Set part number 30000 90076 Update 1 adds troubleshooting information to ...

Page 5: ... memory module is included in this section to assist in troubleshooting memory problems Section V Replaceable Parts A list of replaceable assemblies and their part numbers Also included is a list of replaceable cables and their part numbers and miscellaneous items that may require replacement Appendix A Microdiagnostics Instructions for executing the microdiagnostics that are built into the system...

Page 6: ...A or B or C Lowercase italics denote a parameter wnich must be replaced by a user supplied variable Example CALL name name one to 15 alphanumeric characters Dialogue Where it is necessary to distinguish user input from computer output the input is underlined Example NEW NAME ALPHA1 superscript C return linefeed Control characters are indicated by a superscript C Example yc return in italics indica...

Page 7: ... HP 7920A Disc Drive Verifier SLEUTH07 1 28 HP 30360A Hardwired Serial Interface HSI peA Diagnostic D432 1 30 Section II Page SYSTEM TROUBLESHOOTING Introduction 2 1 Purpose 2 1 MAR 1977 vii CONTENTS Facilities Required 2 1 CPU Register Test Diagnosis and Repair 2 6 Memory Configuration Test Diagnosis and Repair 2 6 CPU Stand Alone Diagnostic Diagnosis and Repair 2 6 Error Correcting Memory Diagno...

Page 8: ...l PCA 30030 60003 4 30 Selectable Trigger Freeze 4 30 Error Logging Register 4 30 Indicators 4 32 Selector Channel Maintenance PCA SCMB 30033 60001 4 32 Configuration 4 32 System Control Panel 30003 60012 4 33 DRT Number 4 33 Memory IC Replacement 4 33 Memory Module 4 34 Preventive Maintenance 4 34 viii Error Correction 4 36 Memory Error Logging Facility 4 39 Output 4 42 Errors 4 44 CE Operating P...

Page 9: ... Maintenance B 41 Wiring Information B 41 Troubleshooting an HP 30312A B 42 Appendix C BATTERY CARE Introduction C 1 Environment C 1 Shelf Life C 1 Restoring Damaged Cells C 2 Shipping Batteries C 2 Summary C 2 TABLES I Table Title Page Table Title Page 1 1 On Line Verification Programs 1 1 1 2 Non CPU Cold Load Diagnostics 1 2 1 3 Diagnostic Tapes 1 3 1 4 System Control Panel Switch and Lamp Func...

Page 10: ...A Switch and Register Locations 4 31 SCMB Jumper Locations 4 33 System Control Panel Jumper Locations 4 34 x 4 22 4 23 4 24 4 25 4 26 4 27 4 28 4 29 4 30 4 31 4 32 4 33 4 34 4 35 4 36 4 37 4 38 4 39 4 40 5 1 5 2 B l B 2 B 3 B 4 B 5 B 6 B 7 B 8 Check Bit Assignments 4 36 Check Bits and Error Code No Error 4 36 Check Bits and Error Error Condition 4 37 Error Logging Array Address Structure 4 38 Erro...

Page 11: ...rification programs and their manual part numbers are listed in table 1 1 Access to the verification programs is obtained by entering the following HELLO FIELD SUPPORT HP 32230 RUN name Table 1 1 On Line Verification Programs PRODUCT NUMBER DIAGNOSTIC DESCRIPTION DIAGNOSTIC MANUAL NUMBER PART NUMBER 30106A 0465 Card Reader 30106 90008 26XX Series L P 0466 Line Printer 30209 90007 2640A 0469 Displa...

Page 12: ...sc File 30102 90015 7900A 0424 Cartridge Oisc 30110 90012 30031A 0425 System Clock Console 30031 90008 300328 0427 Terminal Oata Interface 30032 90011 2660A 0428 Fixed Head Oisc 30103 90015 30030A 0429 Selector Channel 30030 90011 300078 30008A 0430 Fault Correction Memory 30008 90001 30009A 30012A 0431 Extended Instruction Set 30012 90001 30360A 0432 Hardwired Serial Interface 30360 90007 79708 E...

Page 13: ...1017 NOTE 11016 and 11017 are 1600 bpi tapes 1 8 SYSTEM VERIFICATION PROCEDURES The system verification procedures contain the instructions required to execute the diagnostic pro grams Each program is loaded using the Cold Load procedure The verification procedures presented in this section were preconfigured using SDUP If a diagnostic is run that has not been preconfigured operating instructions ...

Page 14: ...ttom half to produce the desired function When released they return to the center position Located behind the upper right portion of the panel are three switches accessible when the cabinet door is opened CPU RESET A two position spring return switch used to reset the circuits of the CPU PANEL DISABLE ENABLE A two position switch that enables or disables the system panel for use PF ARS DISABLE ENA...

Page 15: ...n irrecoverable error detected by the firmware Reverses the run halt condition of the system Must be held in the ENABLE position to permit the LOAD or DUMP switch function to become active Sends the contents of memory and CPU registers to a device specified by internal DRT jumpers Used to load memory from a device specified by the SYSTEM SWITCH REGISTER contents NOTE 1 SWITCHES LOCATED BEHIND FACE...

Page 16: ...00 NOTE The following verification procedures can only be used with tapes shipped with the system and listed in Table 1 2 Unless directed otherwise all operator entries are made using the system console NOTE Prior to performing any maintenance or shutdown procedures have the System Operator verify that all jobs sessions have been terminated before proceeding NOTE Do not power up or power down any ...

Page 17: ...TER P99 05 RESET BOTH PROT DATA SWITCHES SET SWITCH FORMAT AND UNIT TO O Q99 42 WISH TO EXECUTE INTERACTIVE PORTION IN SECTION 1 YES NO D99 07 CARTRIDGE DISC HP 30129A DIAGNOSTIC OFF LINE D419X YY Z 1 14 HP 30008A 30009A FAULT CORRECTION MEMORY DIAGNOSTIC D430 The fault correction memory diagnostic performs the following functions Verifies the Fault Logging Interface FLI PCA array and reads the pr...

Page 18: ...s entry Refer to the following list Memory Word Size Bank Address 64K 0 177777 96K 1 077777 128K 1 177777 160K 2 077777 192K 2 177777 224K 3 077777 256K 3 177777 Press RETURN Program executes and takes approximately 62 minutes to fully test each bank All banks specified above are tested during one pass of the diagnostic NOTE Messages P5 55 through P5 65 will appear when addresses in the range of 1...

Page 19: ...o Selector Channel Maintenance PCA s SCMB should be installed with the correct device numbers before executing the diagnostic Refer to Section IV of this manual for installation information The diagnostic may be run with none or one SCMB installed console messages will be different The following procedure is used to verify operation OPERATOR ACTION COMMENTS CONSOLE MESSAGES Cold load diagnostic D4...

Page 20: ...P2 P02 END SECTION NSGP3 P02 END SECTION NSGP4 P02 END SECTION STPAR P18 1ST SCMB DRT NOT ENTERED STEPS 41 74 ABORTED P19 2ND SCMB DRT NOT ENTERED STEPS 75 78 ABORTED P16 FAST SR READ MODE 2K XFER TIME 4 MSEC BANK 00 STEP 63 P16 FAST SR READ MODE 2K XFER TIME 4 MSEC BANK 01 STEP 63 PI7 FAST SR WRITE MODE 2K XFER TIME 4 MSEC BANK 00 STEP 68 P17 FAST SR WRITE MODE 2K XFER TIME 4 MSEC BANK 01 STEP 68...

Page 21: ...ions of the HP 30110A Cartridge Disc The following procedure is used to verify operation OPERATOR ACTION COMMENTS Cold load diagnostic D424 from stand alone diagnostic tape Press RETURN x Version YY Update level Z Fix level Enter in decimal the DRT number of the disc controller Press RETURN Enter OFF Press RETURN The message means the program has paused and is waiting for an update of the switch r...

Page 22: ...D STEP 101 P03 END STEP 103 P03 END STEP 105 P02 END SECTION 1 POI SECTION 2 P03 END STEP 201 P03 END STEP 202 P03 END STEP 203 P03 END STEP 204 P03 END STEP 205 P03 END STEP 206 P03 END STEP 207 P03 END STEP 210 P02 END SECTION 2 POI SECTION 3 P03 END STEP 302 P03 END STEP 304 P03 END STEP 306 P03 END STEP 310 P03 END STEP 312 P03 END STEP 314 P03 END STEP 316 P02 END SECTION 3 POI SECTION 4 P03 ...

Page 23: ...nnels 0 and 1 on the connector panel Cold load diagnostic D427 from stand alone diagnostic tape Program loads and displays HALT 6 030366 in CIR Select switch register options by setting bit 0 of SYSTEM SWITCH REGISTER off Press RUN CIR displays HALT 7 030367 Enter channel numbers to be tested into SYSTEM SWITCH REGISTER For channels 0 and 1 enter 000001 Press RUN CIR displays HALT 6 030366 Press R...

Page 24: ... HALT 6 030366 Press RUN Program executes and CIR displays HALT 16 030376 after successful completion of test An error condition will display a HALT 12 030372 in CIR Disconnect test cable from channels 8 and 9 and reconnect between channels 10 and II Enter channel numbers to be tested into SYSTEM SWITCH REGISTER For channels 10 and 11 enter 005013 Press RUN CIR displays HALT 6 030366 Press RUN Pro...

Page 25: ...r in decimal the DRT number of the disc controller Enter in decimal the first track to be tested usually O Enter 255 for a 2Mbyte disc or 511 for a 4Mbyte disc Set SYSTEM SWITCH REGISTER bits 0 and 15 on No tracks protected Press RUN CONSOLE MESSAGES DOOO FIXED HEAD DISC DIAGNOSTIC HP 428X YY Z P008 ENTER DEVICE NUMBER P009 ENTER FIRST AVAILABLE TRACK POlO ENTER LAST AVAILABLE TRACK D14 SET SWITCH...

Page 26: ...er in decimal the maximum number of error messages you wish to receive Press RETURN Program executes and displays the following messages CONSOLE MESSAGES NOTE The following console messages were obtained from a system having two memory banks and 128K words of memory D100 HP 30030B SELECTOR CHANNEL DIAG D429X YY Z Q104 SELECT OPTIONS Q101 SET MAINT CARD DEV NUM Q102 SET TIMER CONSOLE NUM Q108 ENTER...

Page 27: ...it 0 off Press RUN Set SYSTEM SWITCH REGISTER bit 0 off Press RUN Program execute and displays the following message Execution time for 200 passes is approximately 60 seconds Program halts after 200 passes CONSOLE MESSAGES DOl HP 30012A EXTENDED INSTRUCTION SET DIAG NOSTIC D431 X YY ZZ QOl ENTER SWREG SELECT OPTIONS Q02 ENTER SECTION SELECT OPTIONS D02 200 PASSES COMPLETED 1 23 HP 30115A NINE TRAC...

Page 28: ...TCH REGISTER off Press RETURN Program executes and message appears on the console after a complete pass approximately 20 minutes for 100 feet of tape Program will repeat until HALT is pressed CONSOLE MESSAGE Q012 MAXIMUM ERROR PRINT COUNT P005 TYPE FOLLOWING CONTROL A CR AUTO E CR EXIT R CR RESTART M CR MANU CR RESUME YOUR CODE D015 PRESENT SECTION REGISTER 077414 DO YOU WISH TO CHANGE YES NO Q019...

Page 29: ... diagnostic The following procedure is used to verify operation OPERATOR ACTION COMMENTS CONSOLE MESSAGES Set the SYSTEM DC POWER switch to STANDBY Discon nect the cable for the peripheral device from the PCA to be tested Remove the PCA to be tested from the card cage and note the position of the interrupt jumper If a TTL PCA also note the presence or absence of jumper WI present positive true abs...

Page 30: ...A 30050 60003 Press RETURN Enter NO Press RUN Enter 2 3 4 5 6 7 8 9 10 Include section 1 only when the test equipment referenced in the manual of diagnostics is avail able for use Press RETURN Enter YES if the PCA is the interface for the card reader punch Otherwise enter NO Press RETURN Time for one pass is approximately 50 seconds Program restarts and continues to run until the operator presses ...

Page 31: ...in CIR Select switch register options by setting all bits of SYSTEM SWITCH REGISTER off Press RUN CIR displays HALT 7 030367 Enter channel numbers to be tested into SYSTEM SWITCH REGISTER For chan nels 0 and 1 enter 000001 Press RUN CIR displays HALT 6 030366 Press RUN Program executes and CIR displays HALT 16 030376 after successful completion of the test An error condition will display a HALT 12...

Page 32: ...ess RUN Program executes and CIR displays HALT 16 030376 after successful completion of test An error condition will display a HALT 12 030372 in CIR Disconnect test cable from channels 8 and 9 and reconnect between channels 10 and II Enter channel numbers to be tested into SYSTEM SWITCH REGISTER For channels 10 and 11 enter 005013 Press RUN CIR displays HALT 6 030366 Press RUN Program executes and...

Page 33: ... procedure is used to verify operation OPERATOR ACTION COMMENTS Cold load diagnostic D439 from stand alone diagnostic tape Press RETURN x Version YY Update level Z Fix level Set SYSTEM SWITCH REGISTER bit 0 off Press RUN Program stops and displays HALT 7 in CIR 030367 After installing the connector press RUN Program executes Section I HALT 7 in CIR 030367 Connect plotter cable place plotter power ...

Page 34: ... Y X 05 8 y 048 V X 03 8 7522 18 Figure 1 2 Type 500 Plot Y x Y X 2 Y Y X 2 Y X 07 8 33 8 00 8 32 8 01 8 t Y 2 x Y 2 x 31 8 30 8 x X 2 068 268 Y 2 X y 2 X 358 34 8 V x Y X 2 Y Y X 2 Y X 05 8 378 048 368 038 7522 19 Figure 1 3 Type 6001700 Plot 1 24 ...

Page 35: ...ons that result in interrupts and traps by the CPU The diagnostic is divided into 14 parts Only the first five parts should be run when no HP 30354A Maintenance Panel is connected to the system The remaining nine parts require the mainte nance panel for observing data Refer to the CPU stand alone diagnostic manual 30003 90001 for details ofhow to execute the remaining nine parts ofthe diagnostic T...

Page 36: ...nfiguration 1 30 PAPER TAPE PUNCH VERIFICATION To verify operation of the paper tape punch perform the following steps 1 Log onto the system HELLO FIELD SUPPORT HP32230 2 Set up the punch file command where LDN the logical device name of the tape punch FILE OUT DEV LDN REC 72 I F ASCII 3 Output the numerals alphabet and special characters from the terminal to tape punch using FCOPY RUN FCOPY PUB S...

Page 37: ...Log onto the system HELLO FIELD SUPPORT HP32230 2 Set up the reader file command where LDN the logical device name of the paper tape reader FILE IN DEV LDN REC 72 I F ASCII 3 If the reader is a job accepting device the follC wing entries are required at the system console to make the reader non job accepting REFUSE LDN ABORTIO LDN 4 Use FCOPY to read from the tape reader and write to the terminal ...

Page 38: ...mats disc packs and checks packs for surface damage The program which resides in the field support account must be copied to magnetic tape for subsequent loading after the MPE Operating System is shut down Detailed instructions for loading and running SLEUTH07 can be found in the HP 7920A Disc Drive Verifier SLEUTH07 Manual part number 32230 90002 The following procedure summarizes disc verificati...

Page 39: ...ss HP 30310A Power Supply CONSOLE MESSAGES COMMENTS UNIT SELECT SWITCH TEST 0 N 1 Y ENTER UNIT SET SWITCH TO UNIT ENTERED PRESS RUN ENTER UNIT SET SWITCH TO UNIT ENTERED PRESS RUN ENTER UNIT TO BE TESTED FORMAT PACK O N 1 Y VERIFY PACK O N 1 Y VERIFY LONG PASS O N 1 Y BEGIN FORMAT END FORMAT BEGIN VERIFY VERIFY PASS 1 VERIFY PASS 2 VERIFY PASS 3 END VERIFY Takes about 10 minutes For short and long...

Page 40: ...o 30360 60003 to TEST for the channel to be tested OPERATOR ACTION COMMENTS Cold load diagnostic D432 from stand alone diagnostic tape Press RETURN x Version YY Update level Z Fix level Set SYSTEM SWITCH REGISTER bit 0 off Press RUN Program restarts and continues to run until operator presses HALT 1 30 CONSOLE MESSAGE HP 30360A HARDWIRED SERIAL INTERFACE DIAGNOSTIC D432X YY Z ENTER SWITCH REG OPTI...

Page 41: ...ly the Semiconductor Memory Array PCA 30008 60002 and the Fault Correcting Array PCA 30009 60001 are repaired to the component level Replacement of the memory array chips can only be performed by those specifically trained in this procedure Attempting replacement by non trained personnel can ruin the PCA NOTE Only IC memory chips marked with HP part number 5080 4560 can be used for replacements Re...

Page 42: ...ECTED RETURN THE SYSTEM TO THE CUSTOMER CALL PRODUCT SPECIALIST FOR ASSISTANCE CALL PRODUCT SPECIALIST FOR ASSISTANCE U EFERTO r PARAGRAPH I 2 10 REFER TO PARAGRAPH I 2 11 STEP THROUGH THE MICROCODE FOR COLD LOAD FROM TAPE l RUN THE MICRO DIAGNOSTIC FOR THE MEMORY CONFIGURATION TEST REFER TO PARAGRAPH I 2 9 I DIAGNOSE AND REPAIR THE PROBLEM j REF R TO I PARAGRAPH 2 4 DIAGNOSE AND REPAIR THE CPU PR...

Page 43: ...SIBLE PATHS EXIST AT THIS POINT IT IS SUGGESTED THAT EACH PATH BE TA KEN IN SEQUENCE AS REQUIRED TO ISOLATE THE PROBLEM AREA WHICH PASS IS THIS 1 2 OR 3 COOLSTART MPE WARMSTART MPE THE FOLLOWING MESSAGES SHOULD APPEAR AT THE SYSTEM CONSOLE CALL PRODUCT SPECIALIST FOR ASSISTANCE Figure 2 1 System Troubleshooting Flowchart Continued DEC 1976 2 3 ...

Page 44: ...ON NO MAKE TWO MORE ATTEMPTS TO GET A SUCCESSFUL COLD DUMP l RE_STARTTHE SYSTEM VIA THE COLD LOAD COOLSTART WARMSTART OR _ _ RELOAD LOG ON THE SYSTEM MOUNT COLD DUMP TAPE ENTER AT CONSOLE RUN DPAN2 PUB SYS CALL PRODUCT SPECIALIST FOR ASSISTANCE ANALYZE THE COLD DUMP ASSISTANCE FROM PRODUCT SPECIALIST MAY BE REQUIRED SEND THE COLD DUMP AND LOAD MAP FOR ANALYSIS RETURN SYSTEM TO CUSTOMER DIAGNOSE AN...

Page 45: ...E NO REFER TO SECTION I System Troubleshooting DIAGNOSE AND REPAIR CPU PROBLEM REFER TO I PARAGRAPH 2 6 DIAGNOSE AND REPAIR MEMORY t t t PROBLEM I REFER TO I PARAGRAPH 2 7 CALL PRODUCT SPECIALIST FOR ASSISTANCE DIAGNOSE AND REPAIR PROBLEM I REFER TO PARAGRAPH 2 8 DEC 1976 Figure 2 1 System Troubleshooting Flowchart Continued 2 5 ...

Page 46: ...st should be continued by pressing RUN so all memory is tested before any repairs are made The N Squared test runs approximately 10 minutes for each 32K words of memory 2 6 CPU STAND ALONE DIAGNOSTIC DIAGNOSIS AND REPAIR The following steps should be performed if the CPU stand alone diagnostic fails 1 If a HALT 12 030372 analyze the halt using the diagnostic listing 2 If other than a HALT 12 perfo...

Page 47: ...ed in paragraph 2 5 2 8 SYSTEM TEST DIAGNOSIS AND REPAIR Information not available at this time 2 9 COLD LOAD PROCEDURE DIAGNOSIS AND REPAIR Information not available at this time 2 10 SYSTEM TEST LOAD Information not available at this time 2 11 COLD LOAD PROCEDURE TAPE This cold load procedure is only valid for ROM PCA s having a date code of 1630 The following is the SIO program built by the mic...

Page 48: ...cks using the CLOCK SINGLE CYCLE switch until the CPU LORQ lamp comes on 60 clocks 7 Release the LOAD switch The SINGLE CYCLE REGISTER DISPLAY switch must be in the REGISTER position up to display the Selected Registers given in the following listing The following conventions are used throughout the listing don t care o zero in display Clocks are counted in decimal all other numbers are in octal 2...

Page 49: ... 94 DIRECT ACTIVE 1726 1206 0 SERVICE OUT FREEZE 95 DIRECT ACTIVE 1726 1206 0 SERVICE OUT FREEZE 96 DIRECT ACTIVE 1726 1206 0 SERVICE OUT FREEZE 97 DIRECT ACTIVE 1726 1206 0 SERVICE IN FREEZE 98 DROP CPU FRZ 1726 0 0 99 1727 0 0 100 DATA POLL 1730 0 0 RESULTS OF HSREQ 101 DATA POLL 3273 0 30 102 DATA POLL 3274 1000 30 00 c t l S t 3 1 1 o C l o o c t s JQ ...

Page 50: ...04 SIO ACTIVE 3276 1000 30 0 30 DRT REQ I O SELECT I O WAIT 105 SIO ACTIVE 3277 1000 30 0 DRT REQ I O WAIT 106 SIO ACTIVE 3275 1000 30 0 DRT REQ I O WAIT 107 SIO ACTIVE 3276 1000 30 0 31 DRT REQ 108 SIO ACTIVE 3277 1000 30 31 NO DRT STORE BAD lOP DRT REQ lOB ENABLE DRT STORE 109 SERVICE OUT 3275 1000 30 31 31 SIO ACTIVE DRT REQ lOB ENABLE DRT STORE I O LOW REQ en 00 S en 3 ...

Page 51: ... O HIRQ I O SELECT 111 SIO ACTIVE 3277 0 30 33 31 33 DRT DOESN T SET BAD lOP DRT REQ lOB ENABLE DRT STORE I O SELECT 112 3275 0 30 33 0 113 DATA POLL 3276 0 30 33 0 114 DATA POLL 3277 0 30 33 0 115 DATA POLL 3275 0 30 33 31 116 SERVICE IN 3276 0 31 33 0 SIO ACTIVE I O LORQ 117 SIO ACTIVE 3277 0 31 33 0 31 I O WAIT I O SELECT 118 SIO ACTIVE 3275 0 31 33 0 I O WAIT 00 Il t 3 I C g g l Il o o c t S J...

Page 52: ...121 SIO ACTIVE 3275 0 31 33 14000 lOB ENABLE 122 SERVICE OUT 3276 0 31 33 14000 SIO ACTIVE lOB ENABLE 123 SERVICE IN 3277 0 31 33 14000 SIO ACTIVE lOB ENABLE 124 3275 0 31 33 0 125 DATA POLL 3276 0 31 33 0 126 DATA POLL 3277 0 31 33 0 127 DATA POLL 3275 0 31 33 32 128 SERVICE IN 3276 0 32 33 0 SIO ACTIVE I O LORQ 129 SIO ACTIVE 3277 0 32 33 0 32 I O WAIT I O SELECT rn c CI l I S rn I o I ...

Page 53: ...IT 132 SIO ACTIVE 3277 0 32 33 0 0 I O WAIT 133 lOB ENABLE 3275 0 32 33 0 SIO ACTIVE 134 SERVICE OUT 3276 0 32 33 0 SIO ACTIVE lOB ENABLE 135 SERVICE IN 3277 0 32 33 0 SIO ACTIVE lOB ENABLE 136 3275 0 32 33 0 137 DATA POLL 3276 0 32 33 0 138 DATA POLL 3277 0 32 33 30 139 DATA POLL 3275 1000 32 33 30 140 SERVICE IN 3276 1000 30 33 0 SIO ACTIVE DRT REQ I O LORQ 00 t rn S o g CD o o e t s ...

Page 54: ...T REQ I O WAIT I O SELECT 142 SIO ACTIVE 3275 1000 30 33 0 DRT REQ I O WAIT 143 SIO ACTIVE 3276 1000 30 33 0 DRT REQ I O WAIT 144 SIO ACTIVE 3277 1000 30 33 0 33 DRT REQ I O WAIT 145 SIO ACTIVE 3275 1000 30 33 33 DRTREQ lOB ENABLE DRT STORE 146 SERVICE OUT 3276 1000 30 33 33 SIO ACTIVE DRT REQ lOB ENABLE DRT STORE I O LORQ t I l c t 1 S 00 1 3 1 ...

Page 55: ... STORE I O HIRQ I O SELECT 148 SIO ACTIVE 3275 0 30 35 33 35 DRT REQ lOB ENABLE DRT STORE I O SELECT 149 3276 0 30 35 0 150 DATA POLL 3277 0 30 35 0 STATE A 151 DATA POLL 3275 0 30 35 0 152 DATA POLL 3276 0 30 35 33 153 SERVICE IN 3277 0 33 35 0 SIO ACTIVE I O LORQ 154 SIO ACTIVE 3275 0 33 35 0 I O WAIT I O SELECT 155 SIO ACTIVE 3276 0 33 35 0 I O WAIT rn S s 0 CD o o s J Q ...

Page 56: ...SIO ACTIVE 3276 0 33 35 40000 lOB ENABLE 159 SERVICE OUT 3277 0 33 35 40000 SIO ACTIVE lOB ENABLE 160 SERVICE IN 3275 0 33 35 40000 SIO ACTIVE lOB ENABLE 161 3276 0 33 35 0 162 DATA POLL 3277 0 33 35 0 STATE B 163 DATA POLL 3275 0 33 35 0 164 DATA POLL 3276 0 33 35 34 165 SERVICE IN 3277 0 34 35 0 SIO ACTIVE I O LORQ 166 SIO ACTIVE 3275 0 34 35 0 34 I O WAIT I O SELECT r n rn S S r n t C l t ...

Page 57: ...69 SIO ACTIVE 3275 0 34 35 0 6 I O WAIT 170 810 ACTIVE 3276 0 34 35 6 lOB ENABLE 171 SERVICE OUT 3277 0 34 35 6 SIO ACTIVE lOB ENABLE 172 SERVICE IN 3275 0 34 35 6 SIO ACTIVE lOB ENABLE 173 3276 0 34 35 0 174 DATA POLL 3277 0 34 35 0 175 DATA POLL 3275 0 34 35 30 176 DATA POLL 3276 1000 34 35 30 177 SERVICE IN 3277 1000 30 35 0 SIO ACTIVE DRT REQ I O LORQ en en S S t 3 o g D en r o o c t s JQ ...

Page 58: ... REQ I O WAIT I O SELECT 179 SIO ACTIVE 3276 1000 30 35 0 DRT REQ I O WAIT 180 SIO ACTIVE 3277 1000 30 35 0 DRT REQ I O WAIT 181 SIO ACTIVE 3275 1000 30 35 0 35 DRT REQ I O WAIT 182 SIO ACTIVE 3276 1000 30 35 35 DRT REQ lOB ENABLE DRT STORE 183 SERVICE OUT 3277 1000 30 35 35 SIO ACTIVE DRT REQ lOB ENABLE DRT STORE I O LORQ rn g S rn I 3 j I ...

Page 59: ...ORE I O HIRQ I O SELECT 185 SIO ACTIVE 3276 0 30 37 35 DRT REQ lOB ENABLE DRT STORE I O SELECT 186 3277 0 30 37 0 187 DATA POLL 3275 0 30 37 0 188 SERVICE OUT 3276 0 30 37 0 DATA POLL 189 DATA POLL 3277 0 30 37 35 190 SERVICE IN 3275 0 35 37 0 SIO ACTIVE I O LORQ 191 SIO ACTIVE 3276 0 35 37 0 I O WAIT I O SELECT 192 SIO ACTIVE 3277 0 35 37 0 I O WAIT fIl g S o g I o o c s JQ ...

Page 60: ...0 WAIT 195 SIO ACTIVE 3277 0 35 37 77740 lOB ENABLE 196 SERVICE OUT 3275 0 35 37 77740 SIO ACTIVE lOB ENABLE 197 SERVICE IN 3276 0 35 37 77740 SIO ACTIVE lOB ENABLE 198 3277 0 35 37 0 199 DATA POLL 3275 0 35 37 0 200 DATA POLL 3276 0 35 37 0 201 DATA POLL 3277 0 35 37 36 202 SERVICE IN 3275 0 36 37 0 SIO ACTIVE 1 0 LORQ 203 SIO ACTIVE 3276 0 36 37 0 36 I O WAIT I O SELECT 00 S en l n l ...

Page 61: ...ACTIVE 3277 0 36 37 37 lOB ENABLE 208 sla ACTIVE 3275 0 36 37 37 SERVICE OUT lOB ENABLE 209 SERVICE IN 3276 0 36 37 37 SIO ACTIVE lOB ENABLE TAPE SHOULD MOVE INTRPT REQ 210 INTRPT POLL 3277 6 36 37 0 211 INTRPT POLL 3275 6 36 37 0 INTRPT ACK 212 INTRPT ACK 3276 0 36 37 0 EXT INTRPT 213 EXTINTRPT 3277 0 36 37 0 214 EXTINTRPT 3300 0 36 37 0 215 EXT INTRPT 3301 0 36 37 0 OPERATION SHOULD BE COMPLETE ...

Page 62: ...j j j j j j j j j j j ...

Page 63: ...he Maintenance Panel is not intended for programmers A software debug package is available for programmers use The Maintenance Panel has a self test capability which allows the operability of most circuits in the Maintenance Panel to be verified without the use of test equipment 3 2 ITEMS SUPPLIED The items making up the HP 30354A Maintenance Panel are the following Maintenance panel assembly moun...

Page 64: ...ROTECTIVE COVER OVERLAY 30354 80010 30354 80015 CABLE 30354 60013 PCA SEPARATOR CABLE STORAGE FOR CABLES 30354 60005 30354 60007 CHASSIS AND PCA WITH I O OVERLAY 30354 80012 Figure 3 1 HP 30354 Maintenance Panel 3 2 DEC 1976 ...

Page 65: ...SYSTEM PARITY lines 2 SYSTEM PARITY lamp Indicates the state of the parity bit generated from the TO FROM and MOP codes 2 TO 0 TO 1 TO 2 Display the address for which the word on the CTL bus is intended lamps 2 FROM 0 FROM 1 Display the address of the module from which the word on the CTL FROM 2 lamps bus is being sent 2 MOP 0 MOP 1 lamps Display the memory operation code This code is used by the ...

Page 66: ...ical registers 4 SKIP lamp Indicates a skip condition is met during the current clock cycle 4 NOP 2 lamp Indicates the state of the NOP 2 bit When true causes a no opera tion by Rank 2 of the ROM Output Register 4 REPEAT lamp Indicates the Repeat bit is true causing the microprocessor to repeat the current microinstruction until the skip condition is met 4 ALU CARRY lamp Indicates the carry signal...

Page 67: ...puts of the V Bus are turned off caused by anyone of the following CPU Reset PWR ON UGATE on RAR in the Store Field INTG on A CPU interrupt is forcing the V Bus to address 3 The execution of a V Bus jump with panel switches 5 5 5 5 5 5 5 5 5 BNDV lamp LUT GATE lamp INTRPT GATE lamp U GATE lamp RAR GATE lamp SAVE GATE lamp JUMP 1 GATE lamp JUMP 2 GATE lamp JUMP FREEZE lamp Indicates a memory instru...

Page 68: ...ll I l rYln I I II I L I A I I t JI 6 INTRPT ACK lamp 6 EXT INTRPT lamp Indicates a response to an lOP Service Out or Data Poll Indicates the lOP has received a request for a transfer to or from memory Indicates a multiplexed I O operation is in progress Indicates the lOP is executing an inbound memory transfer Indicates the lOP has received a request from an SIO multiplexer to fetch a DRT entry I...

Page 69: ...e address being executed 9 V BUS COMPARE These switches specify the microprogram address at which a REGISTER 0 through V TRIG pulse will be supplied The pulse is available at test 15 bistable switches point E3 at the front of the MPI PCA It is also available at pin 3 J3 on the MPI PCA These switches also specify a microprogram jump address or halt address when the V BUS COMPARE ENABLE INHIBIT swit...

Page 70: ...ts the microprogram after A halt brought about by the V BUS COMPARE REGISTER switches A freeze brought about a CCPX 14 special field micro instruction When this switch is pressed the microprogram jumps to the address in the V BUS JUMP REGISTER switches This function should be used only when the computer is halted Selects the REGISTER DISPLAY lamp readout as follows With the switch at the REGISTER ...

Page 71: ...iously ignored interrupts are processed The switch performs no function when the com puter is halted 11 lOP SINGLE STEP Enables or disables the lOP SINGLE STEP EXECUTE switch ENABLE INHIBIT bistable switch 11 lOP SINGLE STEP When enabled by the switch listed above the lOP executes one EXECUTE spring return step each time the switch is pressed switch 11 RESET CPU spring The CPU and MCU are reset wh...

Page 72: ...of a divide by four action in the CPU provides a 175 nsec computer clock cycle The external clock pulse is supplied to a BNC type connector on the CPU backplane The connector is labelled EXT CLOCK A 50 ohm termination impedance is provided in the CPU In the INHIBIT position this switch permits the CPU to execute one machine cycle each time the CLOCK SINGLE CYCLE switch is pressed In the FREE RUN p...

Page 73: ...ommand is displayed in positions 5 through 7 the device number is in positions 8 through 15 Positions 0 through 4 of the display do not light 100 display only Displays via the S bus the contents of the 10D input register lOP display only Displays the contents of the data in register I O DATA display only Displays the data on the 100 0 15 bits On the lOP bus these bits are in not form however the n...

Page 74: ...14 and B15 will be zero RC displays the contents of the third stack register B14 and B15 will be zero RD displays the contents of the fourth stack register B14 and B15 will be zero STATUS displays the CPU status register PB displays the PB status register in REGISTER DISPLAY 0 15 B14 and B15 display the PB bank register P displays the P register in REGISTER DISPLAY 0 15 B14 and B15 display the PB ...

Page 75: ...ough 15 B15 and TION lamp The REGISTER DISPLAY lamps also indicate the data B14 lamps which will be loaded by the LOAD REGISTER MEM ADDRS FROM DISPL switch 14 SWITCH REGISTER Switches 0 through 15 provide a 16 bit word to othrough 15 B15 and B14 bistable switches Load in a selected register by means of the LOAD REGISTER FROM SWITCH RGTR switch Store in memory by means of the MEMORY STORE switch Us...

Page 76: ...ring a system halt caused by an irrecoverable error Lighted when the CPU is running When pressed the register indicated by the lighted REGISTER SELECTION lamp is loaded with the contents of the SWITCH REGISTER switches The bank registers may also be loaded as explained in the SWITCH REGISTER description above When pressed the memory address register SPO is loaded with the bits displayed by the REG...

Page 77: ...ss register SPO The memory address register SPO is incremented or decre mented by 1 if one of the ADDRESS CONTROL switches is at ENABLE A carry from SPO does not enter the ABS bank register 16 BREAKPOINT READ In the ENABLE position this switch halts the CPU when a 16 bit ENABLE INHIBIT word read from memory is the same as the word i the SWITCH bistable switch REGISTER 0 15 switches 16 BREAKPOINT W...

Page 78: ...emented during A When pressed this switch resets the CPU and the I O system Stores in memory from an I O device specified in the SWITCH REGISTER switches Pressing this switch halts the CPU if it is running or starts the computer if it is halted Both halves of a stack op instruction are always completed before the halt takes place If the CPU halts while an SIO operation is in progress the SIO opera...

Page 79: ...INSTR WAIT EXECUTE o o 8 o o o o o RAR GATE OPND WAIT XFER INTRPT INTRPT INTRPT EXT ERROR REO POLL ACK INTRPT 110 DATA SW RGTR SINGLE INSTR o o 8 o o o o o U GATE CPU TIMER 110 TIMER o o o 8 o o o ALU OVFL o INTRPT GATE o o o BREAKPOINT o o o o o 8 LUT GATE lOB DRT ENABLE STORE READ WRITE ENABLE ENABLE CMD DEV NO V BUS o o o ION o o o o 8 o Q BNDV SWITCH REGISTER 6 7 REGISTER DISPLAY REGISTER SELE...

Page 80: ...ressed down when their function is re quired When released they return to the up position Three position spring return switches These switches have a center offposition They are pressed up or down to produce the desired function When released they return to the center position All switches of this type are in row 12 of figure 3 2 Lamps which display register contents are lighted when the particula...

Page 81: ...he SWITCH TEST position This prevents Maintenance Panel switch information from entering the computer system Note that if a power failure occurs with Sl at SWITCH TEST the switch must be returned to the NORMAL position to permit initialization of the computer system for restart after power is restored 3 10 SWITCHES AND INDICATORS ON BAY 1 CONTROL PANEL When the Maintenance Panel is in use switches...

Page 82: ...ANCE PANEL INTERFACE PCA 30354 60003 J1 J2 J3 INTERFACE CABLE 30354 60007 7522 5 FLAT CABLE 30354 60013 TOJ3 REAR OF BAY 1 TO J2 OF CIR PCA A8 POWER CABLE 30354 60005 J2 MAINTENANCE PANEL Figure 3 4 Connections for Use 3 20 ...

Page 83: ...rlay A ticket punch is a suitable device for making the holes in the cardboard 3 14 MAINTENANCE PANEL TEST The following test checks the operability of most circuits in the Maintenance Panel Most circuits in the MPI PCA are not checked If performed as described and if step a below has previously been completed the test can be executed without interfering with normal computer functioning Switch inf...

Page 84: ...nel can be tested by placing the switch on the MPI PCA to the SWITCH TEST position This routes the switch information back to the maintenance panel to be displayed by lighting or extinguishing one or more lamps for each switch The data from the switches will be displayed by nine groups of lamps See figure 3 5 The information for the REGISTER SELECTION switches is coded into six binary bits These b...

Page 85: ... lamps will be illuminated For example 1 8 and 9 8 signify that group 1 lamp 8 and group 9 lamp 8 will be illuminated when the switch is exercised the lamps will extinguish when the switch is off The reverse condition applies to the two position spring return switches extinguishing the lamps when the switch is exercised When exercising the REGISTER SELECTION switches a binary coded value is presen...

Page 86: ...TER SELECTION SWITCHES 2 0 10 0 2 1 10 1 2 4 10 4 2 5 10 5 2 6 10 6 2 7 10 7 2 8 10 8 2 9 10 9 2 13 2 14 10 13 10 14 Q Q Q Q 0 Q 0 0 a Q Q 2 2 2 3 2 10 2 11 2 12 2 15 10 2 10 3 10 10 10 11 10 12 10 15 GROUP 12 01 GROUP9 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 42 43 1 2 3 4 5 6 7 10 11 12 13 14 15 16 17 I 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 40 41 20 21 22 23 24 25 26...

Page 87: ...not troubleshoot to the defective component The exceptions are the Semiconductor Memory Array PCA 30008 60002 and the Fault Correction Array PCA 30009 60001 These PCA s are repaired to the component level Repair of these PCA s should only be performed by CE s specifically trained for this task The repair philosophy for the three power supplies HP 30310A HP 30311A and HP 30312A limits field repair ...

Page 88: ...st be enabled for use Discuss the use of this feature with the system manager su pervisor Refer to the System Manager Supervisor Reference Manual 30000 90014 for a description and use of log files 4 6 MEMORY ERROR LOGGING Memory logging is always activated when MPE is initialized The logging process is automatic and requires no operator intervention To examine the log file a user with system manag...

Page 89: ...kplane of the CPU card cage NOTE DO NOT connect the digital voltmeter common lead to chassis ground Failure to heed this note will produce erroneous and possibly destructive results 7 Use a small tip screwdriver to reach through the top of the HP 30310A Power Supply to adjust A1R1 until the digital voltmeter displays 5 17 volts 8 Leave the digital voltmeter common lead where it is now but move inp...

Page 90: ... and clear interface can be exercised selectively Also device timeout conditions can be simulated causing a timeout error in the selector channel The following paragraphs contain information for installing and using the SCMB 4 9 JUMPERS Three jumpers must be configured on the SCMB See figure 4 20 They are XW1 This jumper selects whether the SCMB is to be used on the selector channel or the multipl...

Page 91: ...that jumper XWI is properly installed c Refer to the System Support Log and ensure that the SCMB device number is not used by any other device in the system d Install the SCMB in an empty slot on the multiplexer channel bus e Install the interrupt poll for the SCMB f If a second SCMB is to be installed repeat steps a through e g Set the SYSTEM DC POWER switch to ON 4 12 SCMB VERIFICATION The opera...

Page 92: ...ELECT SECTION OPTIONS QIOl SET MAINT CARD DEV NUM QI02 SET TIMER CONSOLE DEV NUM QI08 ENTER UPPER BANK QI09 ENTER UPPER ADDRESS OCTAL QI05 ERR PRINT LIMIT DllO DIRECT 110 TEST D127 DIRECT 110 TEST COMPLETED D130 CONTROL ORDER TEST 4 13 SCMB STATE DISPLAY The state of pertinent signals associated with the SCMB can be displayed on the maintenance panel as follows see figure 4 1 a Connect with a flat...

Page 93: ...15 MAINT PCA TO J3 I I I I I I I OF 1A1 MAINT PNL INTRFC TO DISPLAY lOP BUS DATA LINES 100 0 3 10 11 12 13 14 15 V lOP BUS DATA LINES 522 34 Figure 4 1 SCMB State Display 4 14 PROGRAMMING The principal components illustrated in figure 4 2 comprise the SCMB Like any device controller the SCMB is programmed through the use of direct I O instructions issued by the CPU lOP and through I O program orde...

Page 94: ...B a SIN Instruction Sets the SCMB interrupt request flip flop b CIa Instruction Loads a control word from the TOS into the SCMB control register c SIO Instruction Initiates I O program execution if the channel is inactive The SIO instruction is rejected if the channel is currently active d WIO Instruction Loads a data word from the TOS into the counter buffer e RIO Instruction Sends the contents o...

Page 95: ...rect Control I O instruction or through an I O program Control order If a Control order is used the control word is located in the Control order 10AW location the Control order 10CW is ignored by the SCMB The control word is stored in the SCMB control register Refer to figure 4 3 during the following description of the control word format 4 18 Bit 0 Master Reset This bit if a 1 issues a reset to t...

Page 96: ...IT SERVICE REQUEST CONTROL CODE IGNORE IOCW USE 10AW AS CONTROL 0 0 LOAD IOCW INTO CNTRiBUFFER 0 LOAD 10AW INTO CNTR BUFFER 1 0 LOAD IOCW THEN 10AW INTO CNTR BUFFER 1 HIGH SPEED SERVICE REQUEST USE CNTR BUFFER CONTENTS AS DEVICE NUMBER TERMINATE ON TERMINAL COUNT TERMINATE ON NO COMPARE 1 ION 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 COUNT EOT COUNT TOGGLE OUT XFER COUNT P WRITE STB COUNT TO...

Page 97: ...ntents of the counter buffer to be compared to data words issued to the maintenance PCA during channel execution of a Write order Normally data received during execution of a Write order is loaded into the counter buffer If bit 11 is a I the counter buffer contents remain unchanged If a compare failure occurs the SCMB issues either a Device End signal or a clear interface ie REQ to the channel Whe...

Page 98: ...errupt the 4 35 Bit 3 Interrupt Active This bit is a 1 if the SCMB interrupt circuitry is currently in the active state 4 36 Bit 4 Transfer Error This bit is a 1 if the channel has sent the XFER ERR transfer error signal Bit 4 is cleared by the next SIO instruction or I O Reset 4 37 Bit 5 SIO Enable This bit is a 1 if the channel is asserting the SIO ENABLE signal ie channel inactive 4 38 Bit 6 De...

Page 99: ...if the SCMB has asserted the clear interface ie REQ signal to the channel Bit 12 is cleared at the beginning of the next SIO instruction or by an I O Reset 4 45 PROGRAM EXECUTION See figure 4 5 A simple way to initiate I O program execution with the SCMB is to use the CPU cold load feature Because the SCMB counter buffer is cleared by an I O Reset cold loading from the SCMB causes an unconditional...

Page 100: ... program execution press RESET I O MAINTENANCE PCA DRT MAINTENANCE PCA DEV NO 4 I O PGM PNTR 11 h MEMORY LOCATION I I I DEV NO 4 1 ICTRL I 2 LEFT BYTE I FROM SWITCH 3 IREADI 40 MAINTENANCE PCA 4 1 I I I I I I I 000000 UJ MP 5 IUJMP I CNTR BUFFER I l 1 0 CLR 6 l 000000 RESET 7 L 000000 I I 000002 I I 0000004 I I COLD LOAD 1 0 PROGRAM SERVICE ENGINEER DESIGNED 10 PROGRAM 000006 Figure 4 5 Cold Load ...

Page 101: ...ty of 2K words TOP 1 3 0 79 BOTTOM 2 4 0 80 P1 1 3 79 2 4 0 80 2 4 50 1 3 049 J3 1K I n1K POSITIONS W5 1 2K POSITIONS W8 2K ROM peA 30003 60001 2 4 0 50 1 3 0 49 J2 J1 TOP 2 4 0 50 BOTTOM 1 3 0 049 7522 27 Figure 4 6 ROM PCA Jumper Locations 4 49 SKIP AND SPECIAL FIELD PCA 30003 60002 4 50 SYNC JUMPERS When two CPU s are used in a system CPU number 2 slave must be in sync with the master CPU Jumpe...

Page 102: ... BOTTOM 2 4 8OL J2 1i 4 0 i iiiiiiliiiiiiili o i80 L__ II SKIP AND SPECIAL FIELD PCA 30003 60002 o 7522 26 Jl TOP 2 4 50 BOTTOM 1 3 49 J2 2 4 I 50 1 3 49 J3 2 4 0 50 1 3 049 4 51_ Figure 4 7 Skip and Special Field PCA Jumper Locations S BUS peA 30003 60005 4 52 MEMORY SIZE Selection of the memory size is accomplished by setting a ten position switch on the S Bus PCA position switch on the S Bus PC...

Page 103: ...han NORMAL could cause the wrong memory module to be selected TOP 1 3 79 BOTTOM 2 4 80 P1 S BUS peA 30003 60005 1 3 0 79 2 4 0 80 G 0 o 0 1 T 02 P P4 m J i22 2 4 50r JjJ3 2 4 m 50r BOTTOM 1 3 0 049 1 3 49 1 3 49 7522 25 MEMORY SIZE WORDS S3 1 48K 2 64K 3 80K 4 96K 5 112K 6 128K 7 160K 8 192K 9 224K 0 256K MEMORY MODULE SELECTION 51 AND S2 1 FACTORY TEST POSITION 2 FACTORY TEST POSITION 3 NORMAL 4 ...

Page 104: ...e system jumper W2 on the CIR PCA must be removed to enable the APL instructions TOP 1 3 79 1 3 79 BOTTO 1 2 n4 n iiiimrmiiiiiiiiiiiiiiiii1iiiiiion8 oL 2m 4 0 iiJ iiiiiiiiii mniiiiinmm iiSOL_ CIR PCA 30003 60006 7522 37 J1 TOP 2 4 BOTTOM 1 3 0 J2 2 4 50 1 3 49 J3 2 4 0 50 1 3 49 Figure 4 9 CIR PCA Jumper Locations Jumpers WI through W8 are all installed on the CIR PCA when the EIS PCA is not prese...

Page 105: ...mpers WI0 or Wl1 In a one CPU configuration the CPU is designated as number 1 4 60 CPU MODULE NUMBER The CPU connected to the CTL bus is assigned a module number between 4 and 6 by insertion ofjumpers W13 and W14 The module number 5 normally will be assigned to the CPU 4 61 MCU RESET In a single CPU configuration jumper W8 is removed see figure 4 10 In a dual CPU configuration the capability of ha...

Page 106: ...The remaining switch positions are used only for factory test purposes Inadver tently using a position other than NORMAL could cause the wrong memory module to be selected TOP 1 3 79 1 3 79 BOTTOM 2 4 8 L j20 m4 lii mnmiiiiiiiiiiiiimiiiii i8mO P1 I II __ lOP peA 30003 60008 o o T 02 P P4 g I JJi22 2 4 50r J i33 2 4 50r J BOTTOM 1 3 49 1 3 49 1 3 49 MEMORY SIZE MEMORY MODULE SELECTION WORDS S3 1 48...

Page 107: ...umber in the module insert jumpers in socket XW1 figure 4 12 according to table 4 2 noting the revision level of the PCA E l 0 0 0 0 0 0 0 0 k 2 lloo 2 0v 1 co 0 IOv J 12 10v 0 0 00 0 r i sr _ sl UI 3 I Sr J S r Sr S F I SI U31S lfi U21S r E _ I H sr s11 g s c I J sr j lIJ s UI17 1 I c g Eo s I o sr E s c s __ __ RD SELECT JUMPERS Figure 4 12 SMA PCA Jumper Locations 4 21 ...

Page 108: ...002 4 69 MEMORY MODULE CONFIGURATION To configure the MCL PCA to the memory module size position the individual switches on each switch assembly as shown in table 4 3 Refer to figure 4 13 for the location and designations of switches Table 4 3 MCL PCA Switch Positions Module Size Bank Number 0 1 2 3 0 1 2 3 64K 64K 0 C 0 0 0 0 0 C 64K 1 0 C 0 0 0 0 C 64K 2 0 0 C 0 0 0 C 64K 3 0 0 0 C 0 0 C Ill 1 0...

Page 109: ...7522 39 BANK SELECT 64K 0 1 2 3 MEMORY MODULE NO MEMORY CONTROL AND LOGGING peA 30007 60002 Maintenance Procedures DEC 1976 Figure 4 13 MCL PCA Switch Locations 4 23 ...

Page 110: ...DRT number of 2 Switches S1 and S3 through S7 are always closed S2 is always open See figure 4 14 ORT NO ooCJ c J DC LOCJ C M I NC c J II I II 0 FAULT LOGGING INTERFACE PCA 30009 60002 7522 41 J o 1111111111001111111111111 111111111111111111111111111 L ol 1111111111111 111111111r Figure 4 14 FLI PCA Switch Location 4 24 ...

Page 111: ...RRECTION ARRAY FCA PCA 30009 60001 No switches or jumpers exist on this PCA Figure 4 15 is presented as an aid to physically locate components on the PCA I rI II1I IIIIII III c c c IC MI Ci Dew Figure 4 15 FCA PCA Component Location 4 25 ...

Page 112: ...TRATION SHOWS JUMPERS FOR DEVNO 351 8 GG C3J 8 m rn0 00 mmo 8 00 0 rn m0 mm 00 0 rn 8 2 IT rn rn rn g rn rn o0 00 0 0 mrn iJ J mrn o 0J J Grn02 rnm mrn o o 0 IT rn rn J rn rn GROUP INTERRUPT MASK JUMPER SHOWN IN 0 POSITION CLOCK FREQUENCY DIVIDER INPUTS JUMPERS SHOWN FOR NORMAL OPERATING CONDITION INTERNAL BAUD RATE SELECTION SWITCH CR COUNT RATE INPUT JUMPER SHOWN IN INTERNAL POSITION CONSOLE INT...

Page 113: ...clock signal is obtained externally J2 28 and is 16 times greater than the baud rate 4 78 DEVICE NUMBER W7 THRU WI4 The configuration of these eight jumpers deter mines the DRT number usually 3 of the PCA A jumper installed corresponds to a logic 0 and the absence of a jumper corresponds to a logic 1 in the device number 4 79 BAUD RATE SELECTION S1 The PCA can transmit and receive serial data at s...

Page 114: ...238 47 24A 110 48 248 CIRCUlTSIDE 1 35 _ _ _ l 4 ti __ 50 COMPONENT S10E 2ii 4 6ii iiilfiiiiiiim1rmifu L _ lmnIOOiiiiiiimriifu JrinmmiiiiiiimiirihlL _ MULTIPLEXER CHANNEL PCA 30036 60001 J o L oL lIlIlIlIllOllllllllllllllr IIIIIIIIIIIIIIIIIIIIIIIIII 1 111111111111100111111111r COMPONENT SIDE 24 6 50 24 6 50 50 CIRCUITSIDE 135 _ _ W7 t MSB W6 W5 W4 W3 W2 W1 LSB XW1 DEVICE NUMBER 7522 22 Figure 4 17...

Page 115: ...socket to another See figure 4 18 CIRCUITSIDE 135 55 246 _ _ 50 OOM m 246 0 i I__ 3 5 i _ _ XWl XW2 SELECTOR CHANNEL REG ISTE R PCA 30030 60018 o 1 COMPONENT SIDE 2 4 6 CIRCUITSlDE 1 3 5 _ 0 _ XW3 XW4 o CHANNEL NUMBER XWl CHANNEL 1 XW2 CHANNEL 2 XW3 CHANNEL 3 XW4 CHANNEL4 7522 21 MEMORY SIZE WORDS Sl 1 48K 2 64K 3 80K 4 96K 5 112K 6 128K 7 160K 8 192K 9 224K 0 256K MEMORY MODULE SELECTION S2 AND S...

Page 116: ...To use the trigger freeze feature do the following a Set the ten position rotary switch figure 4 19 to the position corresponding to the desired condition b Set the two position switch S2 figure 4 19 to the FRZ position c Initiate program execution d The selector channel operation freezes when the selected condition is decoded by the control PCA e Set the maintenance panel for single cycle operati...

Page 117: ...OR ILLEGAL ADDRESS 2 TRIGGER FREEZE SELECTOR CQMPONFNT 510f 24 6 CIH CUITSl f 1 J _ 1 __ CONTROL PCA 3003060003 SET NO OVER WHITE STRIPE TO SELECT ONE OF THE FOLLOWING O OFF 1 JUMP ORDER 2 RETURN RESIDUE ORDER 3 INTERRUPT ORDER 4 END ORDER 5 CONTROL ORDER 6 SENSE ORDER 7 WRITE ORDER 8 READ ORDER 9 ERROR XERR WRITE CHAINING ERROR READ CHAINING ERROR 16 1 SR TIMEOUT 10 SO TIMEOUT 7522 28 Figure 4 19...

Page 118: ...PCA SCMB was designed to aid the maintenance of the selector channel and multiplexer channel 4 91 CONFIGURATION Three jumpers must be configured on the SCMB See figure 4 20 They are XWI This jumper selects whether the SCMB is to be used on the selector channel or the multiplexer channel A plug in containing two jumper wires is installed in XWl If the jumper wires are aligned with SC on the PCA the...

Page 119: ...t XWI to configure a DRT number and and into socket XW2 to configure a control byte The presence a of jumper signifies a logical 1 By preconfiguring the DRT number and control byte nothing need be entered in the SYSTEM SWITCH REGISTER switches when a system dump is performed See figure 4 21 for the location ofthe sockets 4 94 MEMORY IC REPLACEMENT Replacement of the memory array chips can only be ...

Page 120: ...117 for the preventive maintenance intervals and routines 4 96 Deleted 4 97 MEMORY MODULE The memory module provides high speed storage for the HP 3000 Series II Computer System Memory operates as an error correcting memory with one bit error correction Memory can be made to operate as a non error correcting memory with a parity bit by removal of one PCA However this is not the normal operating mo...

Page 121: ...56K words One MCL PCA can support up to four SMA PCA s 128K words One FCA PCA can support up to 128K words of memory One FLI PCA can support up to 256K words of memory A bank therefore can contain a maximum of 64K words Table 4 7 shows the possible memory configurations available and the total number of PCA s required Table 4 7 Memory Configurations PCA s Required System Bank Word Capacity MCl SMA...

Page 122: ...y word The check bits are actually parity bits calculated over specific bits of the data word See figure 4 22 for the check bit assignments DATA BITS o 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CHECK BITS x x x x x x x X A even parity X X X X X X X X B odd parity X X X X X X X X C even parity X X X X X X X X D odd parity X X X X X X X X E even parity 7522 52 Figure 4 22 Check Bit Assignments During the ...

Page 123: ...en errors are corrected a logic I is stored in a Error Logging Array ELA static 1K RAM located on the MCL PCA The RAM is organized in a 1024 X 1 bit array requiring 10 bits for addressing The five most significant bits of the address correspond to the bank bit 0 and four most significant bits of the memory address that had an error bit The five least significant bits of the error logging array add...

Page 124: ...0 1 Bit 5 0 1 1 0 1 Multiple bit 1 1 1 0 1 Multiple bit 0 0 0 1 1 Bit 15 1 0 0 1 1 Multiple bit 0 1 0 1 1 Bit 10 1 1 0 1 1 Multiple bit 0 0 1 1 1 Bit 12 1 0 1 1 1 Multiple bit 0 1 1 1 1 Check bit I O driver fault 1 1 1 1 1 Check bit I O driver fault Any two or more bit failures in the same address Fault occurred in peripheral circuit BANK MEMORY ADDRESS 10000 ERROR CODE FROM FCA PCA BIT 000 000 00...

Page 125: ...empt cannot be made until the system is brought up again MEMLOGP determines if error correcting memory is present by attempting to obtain the status ofthe FLI PCA DRT 2 Ifthe PCA does not respond error correcting memory is absent from the system and MEMLOGP immediately terminates and no message relating to error logging will appear at the system console If error correcting memory is present the fo...

Page 126: ...ounter in the MEMLOG record for each location where an error occurred 4 Reset the error logging array to a no error condition 5 Write the updated MEMLOG record to disc MEMLOGAN MEMLOGAN PUB SYS is the utility that reads and interprets the error information logged and kept in the MEMLOG file Because of the security placed on the MEMLOG file by the system MEMLOGAN can successfully run from an accoun...

Page 127: ...o a new value and terminates the current interval This causes MEMLOGP to update the memory log file immediately and periodically thereafter according to the new interval specified A new timing interval is specified through the PARM parameter of the RUN command There is no user dialogue with MEMTIMER The PARM value is given as a positive integer greater than zero which represents the number of seco...

Page 128: ... null or updated and if updated whether errors have occurred Ifthe MEMLOG file is null after running MEMLOGAN with PARM 1 MEMLOGAN will terminate after displaying the message NO ENTRIES IN MEMLOG FILE If the MEMLOG file is not empty MEMLOGAN will print the date and time of the first and last log updates If errors have been logged the date and time of the first and last error logged will also be pr...

Page 129: ...T REFERS TO THE FAILING CHECK BIT BOARD SMA SEMICONDUCTOR MEMORY ARRAY BOARD CHECK BIT A ONLY FCA FAULT CORRECTION ARRAY BOARD CHECK BITS B C D E CHIP U N WITH N CHIP NUMBER DATA DATA BIT ERROR OCCURRED BIT 0 15 BIT REFERS TO THE FAILING DATA BIT BOARD SMA SEMICONDUCTOR MEMORY ARRAY BOARD CHIP U N WITH N CHIP NUMBER LOGGING SYSTEM ERROR THIS IS AN ERROR WHICH SHOULD NEVER OCCUR UN LESS THE ERROR L...

Page 130: ... then terminate A non file system error causes the following message to be displayed MEMLOGAN ERROR ERRNUM Where ERRNUM 1 FLOCK ERROR ON MEMLOG FILE 2 FUNLOCK ERROR ON MEMLOG FILE The occurrence of a file system error will cause an error tombstone to be displayed followed by either OUT FILE ERROR or LOG FILE ERROR 4 102 CE OPERATING PROCEDURES The following commands are suggested for the CE to use...

Page 131: ... Figure 4 28 shows the word format for a TIO instruction This instruc tion can be executed any time Bit 0 1 and 2 These bits have the standard I O significance Bit 3 Read Scan This bit is set when a Read Scan is in process and remains set until the completion or termination of the scan Bit 4 DISWEC This bit is set if the disable error correction FF DISWEC is set Bit 5 L ND 128K If bit 5 1 then the...

Page 132: ...arting at the address specified by bits 6 through 15 and finishing at address 1777 The scan is completed when the Address Counter rolls over to 0000 The scan will halt at any I O logging array location containing an error An RIO instruction may be executed to retrieve the address of that error location After the RIO completion the scan will resume During a scan TIO bit 1 0 R W not OK and goes to a...

Page 133: ...0 Data is transferred to the I O logging array in all locations starting at the location specified by bits 6 through 15 and ending at 1777 Upon completion of the transfer the Address Counter is set to 0000 During the transfer TIO bit 1 0 and goes to a 1 two usec after a transfer A Load Block will override simultaneous Write Copy and or Load Single Load Single The data in bit 0 Data is transferred ...

Page 134: ...s is the I O logging array address of a logged error during a Read Scan NOTE The following discussion uses the convention of placing the char acter N before a mnemonic or functional name to signify the not condition RIO I I I I I I0 1 2 3 4 5 671s 9 10 11 12 13 14 15 1 ERROR MSB LSB R WOK y 0 10 BIT ADDRESS READ SCAN DISWEC UU12SK 7522 50 Figure 4 31 RIO Word Format 4 108 INTERFACING 4 109 CTL DAT...

Page 135: ...r 128K MCL PCA A single FLI PCA can communicate independently over the bus to the selected upper or lower 128K MeL PCA 4 112 POWER BUS The CPU applies an ENTIMER signal to the MCL PCA via the power bus to enable a timer during every write cycle If the data is not received within 6 4 msec during a write operation the timer resets the control circuits to prevent memory from waiting for data No loss ...

Page 136: ...1 J1 FAULT CORRECTION r J2 ARRAY PCA J3 30009 60001 J2 J3 MEMORY CONTROL LOGGING PCA 30007 60002 J1 J1 DATA ADDRESSING TIMING l PWRON ENTIMER FRUN CLK IN P1 MCU ClK J PF WARN FRUNCLKOUT P2 P3 CENTRAL CTL DATA BUS I CPU MCU lOP 1 I_O_P_BU_S l 4 7522 43 Removing these PCA s converts memory module to non error correcting mode Figure 4 32 Memory Module Interface Diagram 4 50 ...

Page 137: ...ctivates the appropriate output line to the MCL Error Corrector and complements the bit in error Parity is then calculated on the corrected data bits and sent to the CTL bus with the data When an error has been detected the error code along with the bank bit and four most significant bits CAO A3 of the address containing the error are formed into a ten bit address by the MCL Multiplexer With the e...

Page 138: ...address selects the upper or lower 32K words of memory The remaining 12 bits 04 15 of the address word are applied by the Address Drivers to all of the chips in the memory array However only those chips that have the Chip Enable line active will permit reading out of or writing into that address The polarity of the NR W signal applied to the memory array determines whether the operation is a read ...

Page 139: ...0 I ERROR CORRECTOR J 17 ADDRESS REGISTER DATA OUT 16 16 DATA DATA IN I REGISTER ERROR I I rFCAPCA 1 I 1 CHECK BIT A r 4 I I I CHEC L MEMORY I I I CHECK BIT A 4 4 BIT r ARRAY I I I 16 5 I I I I I CHECK BIT I ra I II ERROR CODE I I PARITY GENERATOR v5 ERROR f ERROR I I I CODE RE iER I I ERROR CODE A E I I L J l _1 5 A D D RE S S BA N K A 0 A 3 _ __ I I I I ADDRESS PARITY GENERATOR CHECKER REFRESH C...

Page 140: ...7 777 TABLE 1 MEMORY ARRAY CHIP CONFIGURATION R W MEMORY ARRAY SEE TABLE 1 R W DRIVER A4 A9 I PM R A10 A15 I ADDRESS DRIVERS CHIP ENABLE LINE DECODER BOARD SELECT JUMPERS AD01 AD03 R W WRITE ClK MEMORY PROTECT READ ClK AD10 AD15 A D04 AD09 0 _ REFRESH ClK JV 1 FROM MCl PCA I O DATA IN 00 15 CHECK BIT A 17 I DATA RECEIVERS DATA IN 17 I 17 I DATA OUT DATA DRIVERS DATA OUT TO 1 17 _ __I MCl I WO 15 C...

Page 141: ...finished its previous operation the Memory Busy Latch will be clear and the Memory Free FF sets with the REFRESH CLOCK signal Under these conditions the Refresh Override Control circuits enable the Address Multiplexer to pass the A10 to A15 address lines to the SMA and FCA PCA s and the ReadlWrite Lockout circuit is disabled to prevent a read or write operation from activating the delay line until...

Page 142: ...ster The Data Address Parity Checker is enabled and checks the address bits with the MCUD PRTYbit for odd parity If a parity error is detected the NMCUD PE line is enabled and the Error Latch is reset forcing a NOP code out of the MOP Decoder The System Parity Checker is enabled and checks the nine control bits TO FROM MOP with the SYS PRTY bit for odd parity A parity error will be indicated on th...

Page 143: ... I I READ WRITE lOCKOUT READ WRITE CLOCK GATE REF RESH CYCLE CONTROLLER A10 A15 DISABLE ADDRESS MUlTIPLEXER WRT DlY START READ DtY START WRITE ClK READ CLK lSB MEMORY FREEFF FROM READ WRITE CIRCUITS REFRESH OVERRIDE CONTROL REFRESH ADDRESS COUNTER 10 BIT REFRESH RATE OSCILLATOR REF RESH ENABLE REQUEST REFRESH FF ADDR J _ I C 11 B 63 63 A t 7 TEMP SENSE INTERNAL EXTERNAL CLOCK SELECTOR 62 A 62 SELE...

Page 144: ...I I I I I I I 00 016 BD0 BD18 I WRIT LOCK I DATA LATCH I W 1 FF 11 __ DATA WRITE DELAY h D4 REGISTER LINE START I 011 E W FF I NOP I I ENABLE 00 MEMORY ENABLE 03 4 I ENABLE I MODULE r I NUMBER FF DATA OUT nDr RWl R W 1 R W FF TIMER CONTROL I 1 16 f COMPARE I 1 CLOCK COUNTER MCUCLK SL Q E IDATA ADDRESS ERROR l PARITY or LATCH CHECKER MCUD HADDRESS AOO AD15 BUS RECEIVERS REGISTER t MCU BUS ENABLE H ...

Page 145: ...a as the FROM module on the bus 4 119 WRITE A write operation MOP 01 will load 16 data bits and a check bit into a given address location Two transmissions to the memory module are required to initiate a write operation On the first transmission the requesting module sends over the CTL bus the address to be written into and the following codes on their respective lines TO FROM MOP MCV PRTY and SYS...

Page 146: ...ed and the NREAD CLOCK signal is applied to the SMA PCA However the output data is not gated to the MCUD lines because the Data Out Drivers are not enabled The set input ofthe Enable FF is disabled by NNOP preventing the Data Out FF from setting preventing the enable from being applied to the Data Out Drivers 4 122 FAULT CORRECTION AND ERROR LOGGING Fault correction and error logging occurs on the...

Page 147: ...J c J1c J c J c J c J c J c J c J c J I 1 I I I I c J I I c J FCA I I c J MEMORY I I ARRAY I I I I I c J c J c J 57 54 c J 55 c J 56 c J c J c J c J I c J c J r J c J ic J c J SO 51 52 53 ARO AR1 LOWER 16K ADDRESSES UPPER 16K ADDRESSES H m en CHECK BITS WRITE ENABLE CHECK BITS READ ENABLE 7522046 r J I I I I I I I I I I I I I I s s s n I o n I p I m Figure 4 37 FCA PCA Memory Array ...

Page 148: ...RROR signal is produced by the Error Detector that activates the Read Write Control Circuit and causes a 1 to be written into the Error Logging Array Errors are only logged during Read and RW1 operations The address where the flag C l is written is determined by a 10 bit address that consists of the 5 bit ERROR CODE three bits of the address read AD01 AD03 and the signals ARO and ARl The fact that...

Page 149: ...R p _ REFRESH ClK _ J r IFCA PCA I I I I TO I SMAPCA L TO SMA PeA FROM SMA PCA J ERROR CODE REGISTER I I I I I I MDl00 15 16 CHECK BIT FROM I f 1 ERROR A_ C H E C K B IT A OODE T PCA I A A GENERATOR SY S T E M 5V y T PARITY CHECK BIT F II GENERATOR I ARO AR1 AD01 AD03 5 ERROR 2 3 CODE I 10 I 1 MULTIPLEXER REFRESH ADDRESS OOUNTER I I I I L I I n ELADf ELAD9 10 ERROR LOGGING ARRAY ERROR CODE 5 f l I...

Page 150: ... I D N I O D OUT a t DIN I LOGGING l RIW ENABLE I ARRAY I a READ COpy p I L U 128K I RIW BUS 1 I ERROR FF I CONTROL SELECT R W r 0 1 1 CONTROL I I I ERROR COMMAND I II DECODER R RW1 I I I RIW TIMING COpy CONTROL MCUCLK I I I 0 I I I REFRESH TIMING L U 128K I I I I I I I I L J P3 L PCA LOWER 128K I SAME AS ABOVE I I I D18 MC D14 L r r IMCl PCA UPPER 128K I I L 7522 51 4 39 FLI peA Functional Block ...

Page 151: ...sables the read and write clocks to the SMA and FCA PCA s Erroneous data could be entered into memory if the clocks were not disabled because TTL circuits oscillate when power to them decays Power failures may be considered as short duration transient line conditions or long duration loss of ac line power A line transient causes the HP 30310A Power Supply to produce the NPFW signal that fires the ...

Page 152: ...are ofbatteries is contained in Appen dix D of the Signal and Power Distribution Manual 03000 90021 4 126 peA JUMPERS Refer to paragraphs 4 66 through 4 72 for details ofjumper installations and switch positions on the SMA FCA FLI and MCL PCA s 4 72 ...

Page 153: ...READ ClK CLOCK GATE I 4 I I rPOWERFAILCIRCUIT 1 I I I I I I PF WARNING I EMITTER 3 5 300 I MSEC MSEC I FOLLOWER I I O S O S I I L J MEMORY I r I _I PROTECT FF I I I EMITTER J r J L PON I I FOLLOWER I DATAIN 16 FROM J JFRUNCLK I I READM RITE I I CIRCUITS I I I I I I I I 5V 8 TO I 5V 8 THRESHOLD TOR ELA I DETECTOR I I I 4 1V CIRCUITS I Pl 55 P1 5 P1 9 PF WARNING MEM PROTECT PON MEM PROTECT PF WARNIN...

Page 154: ...07 Input Output Processor 30003 60008 Multiplexer Channel PCA 30036 60001 Port Controller PCA 30030 6001 6 Selector Channel Register PCA 30030 6001 8 Selector Channel Sequencer PCA 30030 60011 Selector Channel Control PCA 30030 60003 Memory Control and Logging PCA 30007 60002 Fault Correction Array PCA 30009 60001 Fault Logging Interface PCA 30009 60002 Semiconductor Memory Array PCA 30008 60002 H...

Page 155: ...354 60001 30354 60002 Maintenance Panel Interface PCA 30354 60003 Card cage fan 3160 0257 5 3 CARD CAGES Two models of card cages are used in the HP 3000 System HP 30002B and HP 30002C 5 4 HP 30002B CARD CAGE When a fan fails in this card cage both fans must be replaced This requires removal and replacement of the card cage from the equipment bay a time consuming procedure that can take as long as...

Page 156: ... that connects to the card cage then disconnect these cables and wires 7 Disconnect the ground cable and ground plate from the right rear side of the card cage There are two cables and two ground plates if the card cage is not the top or bottom card cage in the equipment bay 8 Remove the angle brace from the left rear ofthe card cage that connects to the adjacent card cage 9 Remove the four screws...

Page 157: ...SYSTEM DC POWER switch ON 21 Ask the console operator to reload the system 5 7 HP 30002C CARD CAGE FAN REPLACEMENT The following procedure is used to replace a defective fan in a HP 30002C card cage Figure 5 2 is used with this procedure 1 Have the console operator terminate all jobs and sessions Have the console operator back up the system files since the system must be shut down 2 Shut down the ...

Page 158: ... located on the bottom left side and be guided by the single plastic guide located on the upper left edge of the card cage CAUTION When inserting the fan chassis into the card cage make certain that none of the fan wires are pinched or otherwise damaged 11 Hold the fan chassis to the left ofthe card cage and secure it to the card cage with the screw and cap washer removed in step 6 12 Replace the ...

Page 159: ...System Service Front View Rear View Figure 5 1 HP 30002B Card Cage 5 6 DEC 1976 ...

Page 160: ... Front View Replaceable Parts DEC 1976 Front View Fans Removed Rear View Figure 5 2 HP 30002C Card Cage 5 7 ...

Page 161: ......

Page 162: ... be interpreted by referring to table A I Occasionally an error causes the computer to halt with the RUN light on and all lights in the CIR display off If this happens press HALT and then use table A I to interpret the resulting coded register number NOTE If the SYSTEM SWITCH REGISTER bit 8 is clear 0 all memory is initialized with HALT 10 instructions 030370 prior to exe cuting the cold load Beca...

Page 163: ...UN HALT switch the CIR then contains the address information shown in table A 2 The test should be continued so all memory is tested before any repairs are made The test is terminated by pressing the HALT switch Table A 2 CIR Address Information CIR BIT FUNCTION 0 3 Address bits 0 3 6 7 Bank number 10 14 CPX1 register bits 2 6 10 2 Illegal address 11 3 CPU timer 12 4 System Parity Error 13 5 Addre...

Page 164: ...es with the device number in CIR The RUN lamp will be illuminated c Press the RUN HALT switch CIR then displays the device status the RUN lamp will be extinguished d Press the RUN HALT switch Steps band c are repeated until all device numbers have been interrogated Diagnostic is finished when CIR displays 000200 The RUN indicator will be extinguished A 3 A 4 ...

Page 165: ......

Page 166: ...adjustments and an occasional troubleshooting The following items are required to perform these tasks A vacuum cleaner for removing dust One digital voltmeter with at least a 4 digit readout and a minimum input resistance of 10 megohms The device should have full scale ranges of 9 999 and 99 99 and accuracy of better than one percent One oscilloscope One multimeter One autotransformer All power su...

Page 167: ...lamp is mounted on the front panel near the test points to monitor the 5 volt output Refer to table B 1 for HP 30310A Power Supply specifications B 3 THEORY OF OPERATION The theory of operation is divided into two sections A general description at the block diagram level is presented first followed by a functional description at the simplified schematic level The power supply converts a 208 240 vo...

Page 168: ...hase 5A or 230V to 240V ac 10 1 phase 5A 47 5 to 66 Hertz 830 watts 1000 volt amperes maximum 5 feet 152 4 centimeters CEE 22 Type VI for ac line CEE 22 Type V for power supply Operating 0 to 55 C 32 to 131 F Non operating _40 to 75 C _40 to 167 F 50 to 95 at 25 C to 40 C 77 to 104 F without condensation Operating 15 000 feet 4572 meters Non operating 25 000 feet 7620 meters 100 cubic feet 2 8317 ...

Page 169: ...ircuit to maintain proper control of the 130 volt DC rail B 8 Inverter A7 The inverter circuits convert the 130 volt DC output of the preregulator to a square wave AC voltage which is transformer coupled to the rectifiers The transformer coupling provides isolation for stages following the inverter The 800 Hertz operating frequency of the inverter is determined by the inverter driver There are two...

Page 170: ...VERTER DRIVER DRIVER 22 AND 9V PART OF A2 PART OF A2 RECTIFIERS T i 2 5V PART OF A8 TWO PHASE 5 VOLT TRIGGER PULSE 22V 22V 9V CLOCK OUTPUT PART OF A2 5V CROWBAR Ir Ir INU INU PON 15V 8 BIAS PREREGULATOR 20V PFW VOLTAGE 15V B COMMON REGULATORS CONTROL A1 FEEDBACK 30V 30V t15V 5V 8 W PARTOF A1 15V 5V VOLTAGE LPU PROTECT A5 5V PSU LINE VOLTAGE MONITOR HE I 4 BIAS VOLTAGES MOUNTED ON 41 6 A2 THRU A5 _...

Page 171: ...pecified limits the paN signal goes low An excessive current overload causes the output DC voltages to drop The undervoltage sequence is initiated due to this condition Circuits also monitor the input AC line voltage If it drops below a preset limit the PFW signal goes low and after a minimum delay of 5 ms the paN signal also goes low When the DC output voltages and AC line voltage are above the s...

Page 172: ......

Page 173: ...15V liAS LINE FREQUENCY IU P GENERATOR F IL TER URI ES _ _ _ SV REGULATOR I BIAS aav SUllS I REGULATOR I PREREGULATOR A9 A9CR I A9R I I f 42 2 l I 00 9Q2 A9CR2 A9R2 I c 42 2 t A9Rl 00 05 560 I A9CRl A9CR4 t I A9AI TI PREREGULATOR II A9L I 01 1 VEl 4 0 TRANSF OItWER II AIL I 115 400 H 1 A8C4 1 AIC5 A8RI T1100 T1100 1 11 25W PREREGULATOR CONTROL AI _ A u I ___t 1 BLOCKING I I OSC ILLATOR I F I 1 1 N...

Page 174: ...I RHE RENCE 30V f t 1 20 OL T I REFERENCE I l A 3 U I _IR_E_ _ _ _ _R 1 _ _ _ A3 I 20 KHZ II URRENT OSCILLATOR A3R6 MONITOR 10K 20V A3R7 1 A3R2B 10K A3R20 6 124K I i_ _ _ _R_T R_ R _ _ _ _ _ _ 1A I _A_3 U_3 _ I F A A ITOR BOAy ABAI I I I I I I 15 VOL T I I RECT IF IERS I I II AeAIR5 ABC2 I I I L _ __ I 5_V A A BJVAIVL_3_ 1 50 _1 3_0_0_0_ _ _ __ I 100 1 15V S 15V PART OF 5 20 VOL T RECTH IER 1 6 r ...

Page 175: ...otect the inverter transistors from short circuit loads The 3200 Hertz inverter driver clock signal is divided to obtain two different 800 Hertz phases phase 1 and phase 2 that are 90 degrees apart Therefore one inverter driver and inverter circuit operates 90 degrees out of phase from the other This results in AC square waves from the inverters which overlap When the inverter transformer outputs ...

Page 176: ...cuits described at the beginning of the paragraph are protected by foldback current limiter action only The 20 and 20 volt outputs are individually protected by current monitor circuits in the 20 volt supply PCA A3 All supply output voltages except for the 20 volts are monitored by overvoltage and undervoltage comparators in voltage protect PCA A5 If an overvoltage condition is sensed a latch is s...

Page 177: ...SENSE signal is provided by a thermistor in the CPU core PON PFW and TEMP SENSE use common W as a return PSU LPU and DCE are provided for use with multiple power supplies They use control common Was a return The 20 and 20 volt outputs use common Was a return and the other DC outputs use common W All four commons are isolated from each other by resistors or an inductor The DC output voltages and th...

Page 178: ... inside the power supply unplug the AC power cable and wait 3 minutes for filter capacitors to discharge To prevent explosion resulting from internal heating always be sure to replace filter capacitors properly with respect to polarity B 16 HIGH VOLTAGE POINTS The highest AC voltage in the power supply is the AC line voltage 250 volts rms 350 volts peak The highest DC voltage in the power supply i...

Page 179: ...d in accordance with the amount of time the power supply is turned off The power supply is not removed from the computer to perform preventive maintenance Preventive maintenance for the power supply consists of the following a Remove dust b Check PCAs for proper seating c Check cooling fan operation d Check the DC operating voltages at the power supply front panel e Check the AC voltages for rippl...

Page 180: ...10A VOLTAGE MINIMUM MAXIMUM RIPPLE VOLTAGE TEST POINT READING READING TOLERANCE 20 See paragraph 8 22 15 14 7 16 5 0 4 volt peak to peak 5 Set at 5 17 0 3 volt peak to peak 5 4 5 5 3 0 3 volt peak to peak 15 14 7 16 5 0 4 volt peak to peak 20 See paragraph 8 22 B 20 HP 30310A ADJUSTMENTS Three adjustments should be made to the power supply after it is installed in the computer These adjustments ar...

Page 181: ...et POWER switch to ON position Increase AC input voltage to 208 volts AC c Connect a voltmeter to terminal El and E2 COMMON 17 on A5 Adjust A5R2 until voltmeter reads 4 22 0 01 volts DC V d Connect multimeter between TB3 pin 5 and TB3 pin 6 COMMON l7 Set multimeter controls to 10 VOLTS DC This monitors the PON signal V e Connect digital voltmeter between TB3 pin 7 and TB3 pin 6 COMMON 17 This moni...

Page 182: ...t power is not available to the power supply Check the fuse b With the power on observe that the 5 volt red indicator is lighted If it is not lighted check that the DCE signal at terminal of TB3 is low and that the indicator is good c Use the procedure given in paragraph B 19 to check the output voltages of the power supply at the test points furnished on the front panel If the voltages are not co...

Page 183: ...f panel covers only the HP 30311A Power Supply The principal parts of an HP 30311A Power Supply are A seven cell sealed lead acid battery pack 30311 60006 A Control PCA 30311 60003 A Motherboard PCA 30311 60002 A heat sink 30311 60005 for the Motherboard Controls and indicators which are mounted on the front panel for monitoring the system refer to figure B 6 A test switch which is mounted on the ...

Page 184: ... and temperature The 20V ADJ potentiometer on the HP 30310A Power Supply must be set fully clockwise Volts 12 7 12 0 1 CD 5 0 2 5 5 0 1 3 0 5 DIMENSIONS Height Width Depth NOTES Amperes O 1 3 6 0 2 0 2 Centimeters 17 8 21 3 36 8 Inches 7 8 375 15 2 CD The 12 0 volt output is adjustable with a 12V ADJ potentiometer on the rear panel o The 12 7 volt output tracks the 12 0 volt output under normal lo...

Page 185: ...ut down the power supply by sensing the 12 0 5 and 5 volt outputs for undervoltage The 3 volt output is sensed for undervoltage to disable the 12 0 and 12 7 volt outputs thus protecting the memory array chips from lack of either 3 or 5 volt substrate bias Overvoltage conditions sensed on the 5 and 12 0 volt outputs cause the power supply to crowbar to protect the TTL elements and memory array chip...

Page 186: ...ATOR REGULATOR I I I I I I I I I I I 0 I r I I I I I I I I 3V AND 5V I I I SERIES REGULATORS I I I I I I I I BATTERY I I STATUS AND I I CONTROL I I CIRCUITS I I OVER UNDER I I VOLTAGE DETECTORS I I r I I I I I I I I L _________ __ J PSU 20V LPU 15V 20V TEMP SENSE HP 30310A POWER SUPPLY 7521 28 EIC_E_ _ _J r 1 SYSTEM D C CONTROL PANEL I J I I Figure B 4 HP 30311A Power Supply Simplified Block Diagr...

Page 187: ...NORMAL SWITCH 3 NO BATTERY BATTERY CHARGE VOLTAGE DIVIDER AND FRONT PANEL 16 45V F1 5A SEVEN CELL I SEALED I LEAD ACID I BATTERY L IT BATTERY INTERLOCK 20V LINE 17 3V NOTES 1 VOLTAGES SHOWN ARE FOR NORMAL OPERATION AT ROOM TEMPERATURE j 22 Cl 2 FUNCTIONS SHOWN SHADED ARE LOCATED ON THE MOTHER BOARD PIN 30311 60002 OR THE HEAT SINK PIN 30311 60005 3 INPUT AND OUTPUT CONNECTIONS ARE VIA BACKPLANE WI...

Page 188: ...The state of the DCE signal is sensed by the DCE detector which controls the battery voltage detector Absence of the DCE signal shuts down the power supply B 33 Internal Supplies A 5 00 volt internal reference voltage is developed from the 16 45 volt level and is distributed to various functional circuits in the power supply This voltage is primarily used for comparison purposes in circuit operati...

Page 189: ... the switch is depressed the crowbar latch is set providing a REGULATOR OVERRIDE signal that effectively forces the 20 volt line to approximately 0 volts Fuse Fl is not opened and the power supply operates from the battery pack as evidenced by the BATTERY STATUS indicator flashing at a 2 Hertz rate and the CROWBAR BATT TEST indicator turning on The computer should be halted before this simulated p...

Page 190: ...0 U ON o OV BATTERY STATUS 0 0 r1 POWER 5A CROWBAR ON ADJ 250V 0 BATT TEST RESET 9 R32 S2 OFF B HP 30312A POWER SUPPLY C HP 30311A POWER SUPPLY 01CAC F15A 250VAC ON POWER OFF PON 20 15 5 000000 20 15 5 COM HEAT SINK 12ADJ 0 BATTERYIk TEST W TOGGLE SWITCH D HP 30310A POWER SUPPLY 8 TEST POINT INDICATOR 1471001 24 E HP 30311A POWER SUPPLY REAR VIEW JAN 1977 Figure B 6 Power Controls and Indicators B...

Page 191: ... follows a Remains continually lit for a fully charged battery b Flashes at a 2 Hertz rate when the battery is discharging c Flashes at a 0 5 Hertz rate when the battery is charging d Remains off if battery is low or not present B 39 HP 30311A MAINTENANCE No high voltage points exist within this power supply However the supply is capable of supplying low voltage at moderate current levels Use caut...

Page 192: ...maintenance consists of measuring the DC voltages at the test jacks on the power supply front panel and performing the battery test procedure described in paragraph B 45 B 44 VOLTAGE CHECKS Measure the five voltages listed in Table B 5 using the digital voltmeter Allow the recommended warm up period for the voltmeter before taking any measurements If any voltage is out of tolerance make the necess...

Page 193: ...within the power supply B 47 BATrERY FLOAT VOLTAGE ADJUSTMENT Float voltage must be adjusted whenever a battery pack is replaced CAUTION The replacement battery pack must be at a stable known ambient temperature before the adjustment is performed For a change in ambient temperature the settling time for the pack is 4 to 6 hours Failure to observe this precaution may considerably degrade the backup...

Page 194: ...float voltage setting h Adjust potentiometer R35 on the control board figure B 7 for the voltmeter indication determined in the previous step This assumes that the battery is almost fully charged If it is not the voltmeter indication will be low and gradually increase as the battery charges A stable indication must exist before R35 can be satisfactorily adjusted i Set switch Sl to position 2 norma...

Page 195: ... 16 08 7 16 89 35 16 05 8 16 86 36 16 02 9 16 83 37 16 09 10 16 80 38 15 96 11 16 77 39 15 93 12 16 74 40 15 90 13 16 71 41 15 87 14 16 68 42 15 84 15 16 65 43 15 81 16 16 62 44 15 78 17 16 59 45 15 75 18 16 56 46 15 72 19 16 53 47 15 69 20 16 50 48 15 66 21 16 47 49 15 63 22 16 44 50 15 60 23 16 41 51 15 57 24 16 38 52 15 54 25 16 35 53 15 51 26 16 32 54 15 48 27 16 29 55 15 45 For 7 cell sealed ...

Page 196: ...ff down b Remove the power supply from the cabinet and place on a suitable support c Remove the top cover from the power supply d Connect the digital voltmeter between the 5 00 volt internal reference test point on the control board figure B 7 and a common ground point on the control board NOTE Allow the digital voltmeter to warm up for the recommended warm up period before taking any measurements...

Page 197: ...pack in the power supply perform the following steps a Remove the power supply from the cabinet by performing steps a through c of paragraph B 51 b Remove the top cover from the power supply c Disconnect jack J7 coming from the battery pack d Remove the battery pack cover plate e Remove the battery pack by lifting it out Install a new battery pack by using the reverse order of the above procedure ...

Page 198: ...rear panel of the power supply c Remove the power supply from the cabinet d Remove top and bottom covers from the power supply e Free the motherboard by removing four screws two from the top and two from the bottom edges of the rear panel frame f Disconnect plug P6 on the motherboard g Slide the two boards out of the rear of the power supply frame h Remove the control board from J1 on the motherbo...

Page 199: ......

Page 200: ...is a simplified block diagram of the HP 30312A Power Supply showing the major functional areas of the interface board The model 62605M Power Supply is also shown to illustrate the relationship between the power supply and the interface board The interface logic is required to properly sense and control the 62605M Power Supply with the existing HP 30310A Power Supply system DC control lines DCE and...

Page 201: ... I I I CURRENT l l 2 SEC CONFIGURATOR TIMER LATCH t OVER CURRENT INDICATOR I P rro INC DEC __ _ U 1 IADJ I R32 I I R26 CAL ADJ Vo S1 CAL TEST I I R51 REF ADJ TURN OFF DELAY 0 15 SEC NOTE 2 TTL INPUT LEVEL ON OFF CONTROL SYSTEM DCE TTL DCE Figure B S HP 30312A Power Supply Simplified Block Diagram Z t c o J J 7521 31 NOTES 1 THIS CONNECTION PHYSICALLY LOCATED AT THE END OFTHE NO 12 AWG CONDUCTORS 2...

Page 202: ...ce board receives the DCE signal and generates the appropriate signal to the Al control terminal on the 62605M Power Supply The interface board circuits delay the turnoff of the 5 volt line after release of the DCE signal by about 0 15 seconds to allow ample time for the HP 30310A Power Supply to generate its PFW signal for the CPU This delay guarantees the 5 volt output will be present for at lea...

Page 203: ...system is down because the 5 volt output of this power supply is absent disconnect the wire at terminal Al of the HP 62605M Power Supply If power is restored the interface board 30312 60002 is defective If power is not restored the HP 62605M unit is bad B 42 JAN 1977 ...

Page 204: ... of its charge in six months A discharged battery has an extremely short shelf life Leaving a battery in a discharged state is by far the most serious cause of cell damage The surfaces of the plates gradually become sulfated with the result that the charge acceptance capability of the cell approaches zero with increases in sulfation Some degrees of cell damage follow A cell left in the discharged ...

Page 205: ...e of the HP 30311A Power Supply be removed when the power supply is shipped or stored This prevents the battery from discharging if the front panel power switch is accidentally tripped during handling A tripped switch causes the battery to discharge fully in three or four days C 6 SUMMARY The HP 30311A Power Supply is designed to power memory and with its battery backup capability to carry the sys...

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