Epson PC AX Technical Manual Download

Page: 1 / 312

Summary of Contents for PC AX

Page 1: ...EPSON pe AX TECHNICAL MANUAL Seiko Epson Corporation Nagano Japan Y12699900201 ...

Page 2: ...n helptul How to Identity and Resoive Radio TV interference Problems This booklet Is avaiiable trom the U S Government Printlng Office Washington D C 20402 Stock No 044 000 00345 4 You can determine whether your computer Is causing interference by turning It off It the Interference stops it was probably caused by the computer or Its perlpheral devlces To further lsolate the problem disconnect elth...

Page 3: ...0 NOT CONNECT THE UNIT TO APOWER SOURCE UNTIL INSTRUCTED TO 00 SO WHEN THE POWER SUPPLY CABLE MUST BE CONNECTED USE EXTREME CAUTION IN WORKING ON POWER SUPPLY AND OTHER ELECTRONIC COM PONENTS WARNING 1 Repalrs on Epson product should be performed only by an Epsan certlfled repair techniclan 2 Make certeln that the source voltage is the same as the rated voltage Iisted on the serial number rating p...

Page 4: ...REVISION ISSUE DATE REVISION PAGE REV A December 1986 REV B September 1988 1 7 2 2 2 6 2 7 2 10 2 15 2 25 2 33 2 36 2 39 2 40 2 42 2 51 2 73 Chapter 8 added ...

Page 5: ...ons and the operating prln clpies of the options TROUBLESHOOTING ProvIdes Instructions for isolating computer mal functlons DISASSEMBLY AND ASSEMBLY Descrlbes system dlsassembly for replacement of malfunctlonlng subassemblles ADJUSTMENT AND MAINTENANCE Usts the necessary adjustments for unlt assembly and servlclng DIAGRAMS AND REFERENCE MATERIALS Descrlbes jumper settings and connector pln asslgnm...

Page 6: ......

Page 7: ...ER 2 PRINCIPLES OF OPERATION 2 1 CHAPTER 3 OPTIONS 3 1 CHAPTER 4 TROUBLESHOOTING 4 1 CHAPTER 5 DISSEMBLY AND ASSEMBLY 5 1 CHAPTER 6 ADJUSTMENT AND MAINTENACE 6 1 CHAPTER 7 DIAGRAMS AND REFERENCE MATERIALS 7 1 CHAPTER 8 DIFFERENCES BETWEEN 10MHz AND 12MHz 8 1 ...

Page 8: ......

Page 9: ...720 Hard Disk Drive Specifications 1 7 HARDWARE CONFIGURATION 1 8 Main System Unit Components 1 8 Keyboard Components 1 12 LIST OF FIGURES Fi gure 1 1 1 1 3 1 1 3 2 1 3 3 1 3 4 1 3 5 1 3 6 1 3 7 Title Major Components ANTA Boa rd ANT Rtl Boa rd SPFG Board ATRPS Unit WHDC Boa rd Floppy Disk Drive Component Keyboard Component LIST OF TAßLES Page 1 1 1 8 1 9 1 10 1 11 1 11 1 12 1 12 Table 1 3 1 1 3 2...

Page 10: ......

Page 11: ...U execution speeds these are the IBN AT speed 6 MHz the new AT speed 8 MHz and a fast er speed 10 l fiIz Speed is selected by setting a three position switch easily accessed from the front The user can see the selected execution speed by the color of a 1ED Wait Cycles EQUITY IlI EPSON PC P f uses several types of internal devices such as RAM ROM 16 bit extension memory 16 bit 1 0 device 8 bit exte...

Page 12: ... has an IBM AT compatible power unit Hs specification is world wide using 115 V 220 V switch selected UL CSA and TUV standard and FCC FTZ standard The number of power cables is 4 Multi function Card The multi function carc in the EPSON proprietary slot provides the serial communication port parallel printer port and floppy disk controller Hard Disk Controller The hard disk controller contained in ...

Page 13: ...3 75 kV 1 min AC Secondary INSOLATION RESISTANCE ElNIRONMENT CONDITIONS 25 MOhm more 500 VDC AC FG AC Secondary 1 MOhm more 250 VDC SG FG DIC short jumper not installed OPERATING Temperature 5 to 35 Humidity 20 to 80 non condensing Maximum wet bulb 29 deg NON OPERATING 20 60 C C to 10 to 90 40 deg STORAGE 5 to 95 45 deg Vibration Shock non HDD Shock HDD Altitude HDD 0 2 G 1 G less than 10ms 1 G le...

Page 14: ...ENSIONS W x D x R 498 5 x 442 x 169 mm WEICHT 14 5 Kg Standard model 1FDD 1 2 2 Keyboard Specifications LAYOUT New AT compatible CORD App rox 2 met ers DIMENSIONS W x D x H 490 x 197 5 x 47 7 mm lmICHT 1 8 Kg 1 2 3 FD1155C Floppy Disk Drive Specification High Density Mode REV A 1 4 Capacity KBytes Unformatted Formatted Transfer Rate K bits sec Number of Tracks Recording Density BPI max MFM FM 1670...

Page 15: ...d Power Consumption x 2 3 ms 15 ms 35 ms 360 RPM 96 TPI HFtl FM 4 8 w 1 2 4 MD5501 61 Floppy Disk Drive Specification Normal Density Mode High Density Mode Capacity KBytes Unformatted Formatted IBM format Lf8 TP I 500 327 7 8 sector 96 TPI 1000 655 4 16 sector 96 TPI 1667 1065 26 sector Transfer Rate Kbits sec 300 Access Time track track ms 10 Recording Density BPI 5876 Number of Tracks p er side ...

Page 16: ...Disks Number of Heads MBytes bytes bytes MBytes bytes bytes bytes Vibration Shock Altitude Transfer Rate 625 KB sec Access Time Track Track 8 ms Average Seek 40 ms Max Seek 75 ms Disk Speed 3600 RPH Start Time 25 sec Stop Time 30 sec Recording Methoc1 MFH Recording Density 9000 BPI Track Density 700 PI Environment Conditions Operatin Temperature 5 4 C Humidity 8 80 29 c 0 2 G 2 0 G o 3000 m Storag...

Page 17: ...ytes Transfer Rate Access Time Track Track Average Seek Max Seek Disk Speed Recording Method Recording Density Track Density Interface 5 Mbits sec 18 ms 69 ms 150 ms 3528 RPH 1 MFM 12900 BPI 910 PI ST 506 412 Temperature Humidity Environment Altitude Conditions Operatin 5 C 50C 8 80 26C 3000 m Storage 40 C 6 fC 8 85 30C 10000 m Shock Vibration No Soft Errors Vibration 0 4 G 36 500 Hz Shock 8 G 10 ...

Page 18: ...port 3 clock channels System clock t calender and CUOS RAM Interface between 80286 and keyboard Controls CPU address bus A16 0 t system addtess bus 5A16 0 and internal address bus XA16 0 Generates refresh address Control bus 1 0 write pulset 1 0 read pu lse t memory wri te pulse memory read pulse and 7 MSB of address bus A23 17 and bus high enable signal Control CPU bus D15 0 system data bus SD1S ...

Page 19: ...P uPD4164 12 27256 EOI090BA E01091EA Qty 18 4 2 2 1 1 FUNCTION 256Kbit dynamic RAM Parity check RAH 64KB x 4 dynamic RAM Parity check RAM BIaS ROM Address decoder for memory space and parity checker generator for system D RA I Generates D RAM address MA8 0 and D RAM access signals RAS CAS and WE FIGURE 1 3 2 ABT RH BOARD 1 9 ...

Page 20: ...A E01093BA E01094BA 16450 Q ty 1 1 Q 1 FUNcnON Controls FDD s Parallel port and address decoder for serial port Controls 360KB and 1 2MB diskette drives Includes FDOR Floppy digital output register FCR Floppy control register and write precornpensation circuit Controls serial data transfer 1 10 FIGURE 1 3 3 SPFG BOARD ...

Page 21: ... PRODUCT DESCRIPTION WMINAL LOAD CURREBT LOAD CURREBT REGULATION OVERLOAD OU1PUT VDC MIN A HAX A TOLERANCE PROTECTION A 5 2 5 20 4 35 5 0 0 3 10 3 12 0 4 8 7 0 5 16 12 0 0 3 10 3 10 sec FIGURE 1 3 4 ATRPS UNIT FIGURE 1 3 5 WHDC BOARD 1 11 ...

Page 22: ...RE 1 3 6 FLOPPY DISK DRIVE COMPONENTS Refer to Chapter 3 for the Floppy disk drive components 1 3 2 Keyboard Components The new IBM AT compatible keyboard with horne posHion keys F J and 5 marked FIGURE 1 3 7 KEYßOARD COMPONENT 1 12 ...

Page 23: ...PERATION System Clock Generation Circuit Select CPU Operation Speed LED Indications Select NPX 80287 Operation Speed Ose 11 ator System Reset Signal Generation Circuit System Reset Circuit Internal Memory Control Circuit RAM Chip Type RAf 1 Chip Addresses Jumper Connector Function Operation of emory Control Circuit Byte Word Access 16 8 Bit Data Conversion Data Bus Control Signal on GAATDB Circuit...

Page 24: ...rection Control Signal Parallel Data Control Circuit 1 0 Address Selection Parallel Data Control Circuit Functions FDD Contral Circuit FDD Control Register Access Circuit Interrupt Signal and DMA Request Signal from FDC FDD Con t ro1 Si gnals Read Wri te Ci rcu it Other Functions KEYBOARD Block Diagram Interface Signal AT t 1ode XT Mode Description of Interface Signals AT Mode Clock Data Keyboard ...

Page 25: ...t of Photocoupler Output Signal Waveform Overvoltage Prevention Circuit Overheating Prevention Circuit Power Good Signal Generation Circuit I Power Good Signal Generation Circuit II Timing Chart of Power Good Signal Internal Circuit Configuration System Clock Supply Circuit Clock Speed Change Circuit System Reset Circuit Internal Memory Control Circuit Byte Word Access 16 8 Bit Data Conversion Dat...

Page 26: ...Other Function Circuit 1 0 Slot Access Signal 16450 Chip Select Circuit 1 0 Address Sel ecti on Data Output Printer Data Register Circuit Output Data Read Ci rcu it Printer Control Signal Output Circuit Printer Control Signal Read Circuit Printer Status Signal Read Circuit Interrupt Signal Control Circuit FDD Control Circuit I FDD CPU Interrupt Signal and D A Request Signal from FDC FDD Data Write...

Page 27: ...GAATRF Jumper J9 Setting Difference Between 1 2 MB FDD of SD 581L and FD1155C t1D5501 Interface Control 1ode Data COJTlllunication r 1ode AT t1ode Data Comnunication t10de XT Mode Data Transmission Method and Data Format Keyboard Connector Pin Function Transmission Intervals Ove rrun Code s Key Code Make Up Condition for Setting and Releasing Numeric Lock Key Stroke Condition Extension Left and Ri...

Page 28: ......

Page 29: ...MAC 8237x2 ANTA board CPU 80286 ANT RM board ANT RM board _M6_E _g_ _ _ I connecJ t_o_r_ __ c_on t 1f1 I TI ER 8254 2 RTC 146818 KEYBOARD controller 8042 8742 INTC 8259x2 keyboard 5 12 5 12 ATRPS unH Power supply unit SPFG board Floppy Parallel Serial disk Printer communication interface interface interface AC outlet HDD WHDC board Hard disk controller RS 232C slots PRINTER FDD CRT 1 Monitor adapt...

Page 30: ...A16654 controls the MOS FET By supplying power to the HA16654 current flows in the liOS FET 2 2 1 1 Power supply circuit Power supply circuit for the HA16654 is explained by the following 2 steps 1 From power on till the transformer for switching oscillates correctly 2 After the transformer for switching has oscillated correctly 1 From POWER ON till the transformer for switching oscillates correct...

Page 31: ...g has oscillated correctly No current is present in RIl t DIO t DII t and DI9 because the voltage supplied from DI2 and RIS is higher than the voltage supplied from Rl1 t DIO t Dl1 and D19 This causes the increase of efficiency of the ATRPS Unit Tl I R11 t I D10 V I I D11 D19 J 7 4 VIN HA16654 9 6 GND FIGURE 2 2 3 SWITCHING OSCILLATION CIRCUIT 11 2 3 ...

Page 32: ...Q4 and Q5 works as foliows If the input voltage is higher than the standard voltage t the Q5 collector current flows instead of the Q4 collector current R11 05 R12 e t FET Q1 Q2 Vin HA16654 OB 7 5 OUT VRef I R2 R6 R3 GND R15 R17 510 2 4 FIGURE 2 2 4 OVERCURRENT PREVENTION CIRCUIT I vce O l 5 1K 10 K GN0 0 FIGURE 2 2 5 OVERCURRENT PREVENTION CIRCUIT 11 ...

Page 33: ...lows 4 If the voltage at the DB terminal in the HA16654 increases and the pulse width is reduced then the current decreases 2 2 1 3 Inrush Current Prevention Circuit The inrush prevention circuit protects diode bridge DBI and subsequent components from being damaged by excessive current flow in C12 and C13 at power up R3 limits the current to RC1 when power is applied when the switching oscillator...

Page 34: ...electromotive force which is in the direction of 1 is produced in the transformer Tl tbe series voltage regulator 21 and 22 are supplied with the power reference through RC2 and L4 When an electromotive force which is in the direction of 2 was produced at the transformer Tl the power reference is supplied from L4 R17 is for capacitor discharge D14 and D13 is for series voltage regulator protection...

Page 35: ...tage stabilization circuit b l Basic Function When a control signal Is high level an electric power through the transformer L5 is decreased This function control the 12 volts voltage T 1 Vo ltage stabilization ci rcuit Control signal FIGURE 2 2 10 12V STABILIZATION CIRCUIT b 2 Voltage Stabilization Circuit The 23 i8 designed so that when the voltage of reference terminal reaches fixed level a curr...

Page 36: ...ltage rises and then the cathode current increases After that the Q3 collector current increases and the Vout voltage decreases Function 1 If the Vout voltage decrease the Vref voltage decreases and the cathode current decreases After that the Q3 collector current decreases and the Vout voltage rises _ _ Function 2 CATHOOE CURRENT A REFERENCE VOLTAGE V FIGURE 2 2 12 CHARACTERIZE OF Z3 2 8 ...

Page 37: ...eed Control Circuit FAN When temperature increases value of resistance decreases TH1 12V GN D FIGURE 2 2 130 FAN REVOLUTION SPEED CONTROL CIRCUIT d Overcurrent Prevention Circuit If a current is supplied more than a fixed current to 12V circuit operational amplifier outputs high level signal and a transistor is turned on Next the DB terminal voltage rises and it causes the voltage of the output te...

Page 38: ...it is shown in Figure 2 2 15 The function of the 5 volts circuit is same as SV circuit and 12V circuit L7 0GND Tl FIGURE 2 2 15 5V SUPPLY CIRCUIT b Voltage Stability Circuit 4 0 5 J GND 5 GND OUT HAI6654 EI R7 Re e Z4 If RVl 2 2 K R32 910 2 10 FIGURE 2 2 16 5V VOLTAGE STABILITY CIRCUIT ...

Page 39: ...6654 The 8th pin error input terminal and the 5th pin output terminal of the HA16654 have the following relation If the voltage of ERROR INPUT terminal rise the pulse width of the output terminal is reduced ERROR INPUT DEAD BAN 0 t I eT11 1 1 11 11 OUTPUT _ FIGURE 2 2 18 OUTPUT SIGNAL WAVEFORM Characteristics of 24 When the reference vo1tage of the IC24 reaches a fixed voltage current flows from c...

Page 40: ...tage of the secondary oscillation circuit increases If the voltage of the stable 5 volts line is lower than 5 volts enlarge the resistor value of volume RVl Then the terminal voltage of R32 decreases and the current flowing in Z4 decreases The voltage of the ERROR INPUT terminal of the HA16654 decreases and it causes the pulse width of the output terminal to widen and the 5V line voltage to increa...

Page 41: ... 2 2 5 Power Good Signal Generation Circuit The pOvler good signal generation circuit monitors the 5V line 12V line 12V line and 5V line of the secondary oscillation circuit If there is an abnormality low voltage in these lines the power good signal changes to low level signal Also it monitors a primary voltage proportion circuit If there is an abnormality low voltage in the input AC adapter power...

Page 42: ...PRINCIPLES OF OPERATION T1 017 I R34 I R35 I I L J R36 REV A R38 lOOK 27 26 FIGURE 2 2 21 POWER GOOD SIGNAL GENERATION CIRCUIT I Primary voltage proportion circuit 2 14 ...

Page 43: ...REV B PRINCIPLES OF OPERATION 12V line 12 5 line 12 line A R38 09 010 R39 R 41 R40 R 42 FIGURE 2 2 22 POWER GOOD SIGNAL GENERATION CIRCUIT 11 2 15 ...

Page 44: ...D SIGNAL TABLE 2 2 1 FUNCTION OF PREVENTION CIRCUIT Detecting voltage or Detecting current Condition after detecting Overvoltage detector SV 12V 12V SV 5 5 volts 7 0 volts Cut all output off To recuperate condition turn off AC then on after 30 seconds Overcurrent prevention circuit SV 12V 12V SV 3sA 16A 3A 3A Cut all output off To recuperate condition turn off AC then on after 30 seconds 2 16 ...

Page 45: ...NTA BOARD 1 23A OA effective value ANT RM BOAHD O 50A OA effective value SPFG BOARD O 54A OA effective value WHDC BOARD O 53A OA effective value HRS MO BOARD O 27A OA effective value MRS CR BOARD O 50A effective value FD1l55C O 46A O 21A TYP O 39A po ler on MD5501 o 1lA TYP o 24A TYP 1 66A peak HMD 720 O 2A TYP 2 0A power on O 58A TYP D5146 40M HDD l OA MAX 3 0A power on 2 0A seek 1 2A read write ...

Page 46: ...PRINCIPLES OF OPERATION REV A TAßLE 2 2 3 POWER DOWN SIGNAL SPECIFICATION Power down signal 11 2 18 11SV MODE 230V MODE 7SV lSOV I 1 AC 75 80 Power down signal I 1 AC 150 160 ...

Page 47: ...cuit of the EQUITY 111 EPSON PC AX computer system There are several blocks in the diagram for each circuit operations ARTA BOARD ART RM BOARD GAATCK CPU n GAATRF I I I I GAATJO GAATMI I I I I I GAATM2 MB81256 0 equivalent MB81256 0 equivalent PD4164 0 eCluivaient jJPD4164 0 eQuivalenl N I I Q GAATDB FIGURE 2 3 1 1NTERlIAL C1RCU1T CONFIGURATION I d CI o I ...

Page 48: ...mory 128 KB video RAM 128 KB r o EXPANSION ROM 64 KB reserved on system 64 KB ROM on system board Maximum memory 15 MB 64 KB reserved on system 64 KB ROM on system board System memory Reserved for graphics display buffer Reserved for ROM on 1 0 adapters Duplicated code assignment at address FEOOOO Duplicated code assignment at address FFOOOO 1 0 channel memory memory expansion option Duplicated co...

Page 49: ... circuit NPX does not divide the input clock signal in 8 filz mode Please refer to Section 2 2 3 This means there are some cases that the input clock speed is not identical with the operation speed This manual defines these words as below Clock speed Input or output clock signal speed Operation speed Internal clock speed 2 3 1 1 Select CPU Operation Speed The EQUITY III EPSON PC AX has three kinds...

Page 50: ...speed modes TADLE 2 3 3 NPX OPERATION SPEED NPX OPERATION SPEED MODES OPERATION SPEED CPU OPERATION SPEED 1 CPU CLOCK MODE nlz SHHz 1000mz 2 8MHz MODE 6NHz SMHz 1 OHHz 4HHz 5 3HHz 6 lNHz 8MHz A selection is performed by setting of jumper connector Jl and J2 on the ANTA board Main circuit board Jumper connector setting of Jl and J2 are listed in CHAPTER 7 REKARK NPX divides the CPU clock into three...

Page 51: ...ignals TABLE 2 3 4 OSCILLA l OR CLOCK SIGNAL FLOW OSC CLOCK SPEED GAATCK DIVIDE l BE CLOCK IN l O GAATCK OU1PUTS CONNECT l O MAJOR CHIP N I N W 48lvlliz 20MHz 14 31818MHz 1 3 1 4 1 6 1 8 1 1 1 1 1 12 16MHz 12MHz 8MHz 6MHz 20HHz 14 31818MHz 1 19l 1Hz CPU CPU NPX KEYBOARD CONTROLLER CPU OPTION SLOT TIMER COUNTER cn ol Zj to j t I o Z ...

Page 52: ...N I N 0 S tl cn o 2 GAATCK 1S01 1SOn CN3 Red ft Green er J 1 r1 ilO 4 t CSPD 0 L L I i t 1 CSPD FIGURE 2 3 2 SYSTEM CWCK SllPPLY CIRCUIT FIGURE 2 3 3 CLOCK SPEED CBAI E CIRCUIT ...

Page 53: ...e the following methods TABLE 2 3 5 RESET SIGNAL GENERATION METHODS 0 trJ t P RESET SIGNAL CPU RESET SIGNAL INTERNAL CIRCUIT RESET SIGNAL OPTION SLOT REST SIGNAL REMARK METHODS 1 PWGD signal goes low 2 Reset switch is pushed 3 Re signal goes active Software reset 4 Shut down cycle is executed Reset switch is pushed Reset switch is pushed N I N Jl The software reset command RC goes active resets on...

Page 54: ...gh level When the gate array GAATCK receives the PWGD signal signal a RSDN signal and a RSCPU signal it generates a RSN tl o l tzj H o iZl 3 RC signal A RC signal is sent from P20 pin of the keyboard controller 8042 which can be controlled by software A RSCPU signal becomes active by the active RC signal Refer to the remark in section 2 4 4 Shut down cycle A Shut down cycle is a kind of CPU execut...

Page 55: ...l s19011 ls 11 lys h19h _ r the res t SII ls PUShed II r J R 5 T 0 I RSTNi DMA2 8237A 5 GAATCB L j RESET L jRESET 10 the fo11owl 9 eondltlon thls slgnel _ leth 1 PIIGO sl9O l _ 10w 2 ReHt SW ls pushed 3 RC 19011 _ s leth 4 Shut down eycl GAATIO GAATM2 i i BltO 1 2 Ind 31 Ire el red RST_ ill 8042 GAATDB Illml N I N J RESET I P201 FIGDRE 2 3 4 PRSI SYSTEM RESET CIRCUIT tl cn o i i6 S i ...

Page 56: ...3 1 RAH Chip type On the ANT P board there are three kinds of RAM chips Refer to Table 2 3 6 TABLE 2 3 6 FUNCTION OF RAH CHIPS RAH CHIP TYPE Q TY FUNCTION 256K word by 1bit 16 System memory 512KB 64K word by 4bit 4 System memory 128KB 256K word by 1bit 2 Parity check 64 K vlO rd by 1bit 2 Pari ty check 2 3 3 2 RAH Chip addresses The system memory RAM chips are located in the following address 09FF...

Page 57: ...D 2 3 3 4 Operations of Memory Contro Circuit 1 ADDRESS SIGNAL The CPU outputs address signal AO to A23 Next the GAATM2 Memory control gate array 2 receives from Al signal to A18 signal to make RM1 chip address signal Also the GAATM1 Memory control gate array 1 receives from A17 signal to A23 signal and AO signal to make a RAS signal a CAS signal and etc REKARK 1 The GAATRF controls A20 signal REK...

Page 58: ...receives MEMR and MEMW signals to control RAS and CAS signals Also GAATM2 recei ves XMWN MEMWN signal which has flowed through GAATCB to make WE signal of the RAM chips GAATMI receives XMRN MEMRN signal which has flowed through GMTCB to make RAS CAS signals 4 RAM CHIP CONTROL SIGNALS All D PJlli control signals are sent from GMTM2 5 D RAM REFRESH CONTROL ClRCUlT Refer to Section 2 3 11 tl cn o t r...

Page 59: ...N I W GAATCK GAATAB GAATRF TO RA CHIP OA TA BUS C FRO RA CHIP FIGURE 2 3 5 INTERNAL MEMORY COBTROL CIRCUIT Used for address sel ct1ng d 8 RA1 CAH CAL 5 tl o I j o tl I l j ...

Page 60: ...ION OF ODD ADDRESS 8 BIT DEVICE Figure 2 3 11 7 WORD TRANSMISSION OF EVEN ADDRESS 8 BIT DEVICE 16 8 BIT DATA CONVERSION 8 WORD TRANSMISSION OF ODD ADDRESS 8 BIT DEVICE Figure 2 3 12 2 3 4 1 Data Bus Control Signal on GAA IDB The GAATDB includes five 8 bit buffers This buffer needs a gate control signal and a direction control signal The following table describes gate control signals and direction ...

Page 61: ...vi th the above steps automatically 5 BYTE TR JSMISSION OF EVEN ADDRESS 8 BIT DEVICE Figure 2 3 10 shows the GAATIlB internal circui t operat ion 6 BllE TR NSHISSION OF ODD ADDRESS 8 BIT DFYICE Figure 2 3 11 and Figure 2 3 12 show the GA TDB internal c rcuit operations Read mode Figure 2 3 11 Write mode Figure 2 3 12 7 WORD TR jSM1SSION OF EVCN ADDRESS 8 B1T DEV1CE 16 8 bit data conversion Figure ...

Page 62: ...t of the GAATRF generates the LSAO signal but not in the conversion mode the GAL TRF uses the CPU AO signal to make LSAO signal The internal buffer LS646 of the GAATDB inputs this signal XAO signal to send the catched data to t he CPU Also the 8 bit device receive this signal to determine address Ifuile a 16 8 bit data conversion this signal changes status as low to high I l tn o fatz l 2i ...

Page 63: ...decordlng signals beeane disabled G24SN XAll nd XIIllE slgn ls r CDFF GAATCK ree oiv s an aeUv ClFF signal 1 C ill the road write signal of GAATCK goss inecUve i DH h DU A GDlN CPU GAATCB signals are r DMD i 1l l output by E Si decoding OTR l5AO nd IM 51 7 815 GAATIO GAATMZ IHE BHE CPU iiüllü BBM tt i OL N J I GAATDB i LI D245 r G245 k GMDHN r 2 GMDlN r s I 024S Equl l nt DMD III 024s Inte 1 Circu...

Page 64: ...E I l G OlN AO H 14015 2 08 J MAD IIRITE HNI IA GOlN l C8A l S8A lAD l I 0245 G245N H u ugu fl i i l H BkA 2 B 4 A 5 DIA i 1401 l 1400 I N I I o l 7 S01 SOO 5015 S08 OPTION SlOT OPTION SlOT FIGURE 2 3 7 DATA TRANSMISSION 1 0 16 BIT DEVICE BYTE TRANSMISSION OF EVEN ADDRESS FIGURE 2 3 8 DATA TRANAMISSION 1 0 16 BIT DEVICE BYTE TRANSMISSION OF ODD ADDRESS AI M tJj ...

Page 65: ...gno Is output Only hen reedtng t internal ry thls slgno goes hIgh I DUS GUSN H DMD 1 1 GMDHN BHE I l G M D l N 1001 l l READ l j i TRI H WRIT SBIo 1001 l Bk I 2 B I 5 DIR C MOlS l 1 MOl 0 0 J w I MOl lMOG OPTION SlOr FIGDRE 2 3 9 DATA TRANSMISSION TO 16 BIT DEVICE WORD TRANSMISSION OF EVEN ADDRESS N I W l SOlS SOl 507 500 507 500 11 blt FIGDRE 2 3 10 DATA TRANSMISSION TO 8 BIT DEVICE BYTE TRANSMIS...

Page 66: ... A B B A S 2 L 8 I A A B 5 5 r ll DIA L L Ji d B S 2 A 8 5 Only l ry UL 1 1 I OMO 1 g gr il I 0245 H G24SN l Dlet I rA 00 DIAll_ GDHN l I N OI H At B S 2 A B 5 r DIA A t B s 2 A B 5 II DIA i N I Shit DEVlC J 8blt DEVIC FIGURE 2 3 11 DATA TRANSMISSION TO 8 BIT DEVICE READ MODE BYTE TRANSMISSION OF OnD ADDRESS FIGURE 2 3 12 DATA TRANSMISSION TO 8 BIT DEVICE WRITE MODE BYTE TRANSMISSION OF ODD ADDRES...

Page 67: ... GUS H 1 GMDlN 4 l 5 01 l O s 01 00 G O H N on Ut 1 At s l A 5 l Jtl L t S l 5 l 0 r I These signal are changed by cha i J the LSAO status from 1 level to high level i g t l CU H 58A H The htcMd date fs I Bhtt O V C otItput on thts d te 001 Dill CPU Odd ddreu d te FIGURE 2 3 13 DATA TRANSMISSION TO 8 BIT DEVICE WORD TRANSMISSION OF EVEN ADDRESS 16 8 BIT DATA CONVERSION READ MODE It OMD l GMOHH lGM...

Page 68: ... if CPU 1 4 5 01 The 8 bit device reads Data 2 cl I OMO l GMDHN l GMOlN l heft ddren date OO N GONN l GOlN l C l se l 01 00 I rc I OUS h I G 5N H CPU 015 0 G al i i i i The 8 bit device reads Data 1 N I oll o 8Mt o Vla hit DUltl Ilbtl Ill YIC FIGURE 2 3 14 DATA TRANSMISSION TO 8 BIT DEVICE WORD TRANSMISSION OF EVEN ADDRESS 16 8 BIT DATA CONVERSION WRITE MODE 0 t r I Cd ...

Page 69: ...and the r o device C cn o o C tz l t I o Z T 8blt 1 0 devlce 1 0 DEV1CE ACCESS C1RCUIT GAATAF 4237A 5 80287 LSAO I eMOO eMD 4 1 3 3 NIIWrl NP51 L NPS2 110 deV1C I 825 2 I 8254 2 146818 GAATIO rff A Vi OS AS cso c POWER r SUPPLY CSDIII SIGNAl CI t eS lII CS d IlCSN CSUN l SA I GAAICB GAATAB GAATOB 0 DIA FIGURE 2 3 15 IO A Io 110 DOWN GAATCK 015 DO 10 GAATRF I oll J I ...

Page 70: ...SCR1PTION 1 0 connections to data and control bus used for reading from and hTi ting to the map register seleeted by RSO RS3 vhen es i s 10w lode eontrolled by R W Register seleet inputs for 1 0 operations Read 01 vri te eontrol used in 1 0 operations to seleet the eondi tion of the data bus hen high the data bus outputs are active for reading the register w hen lOH the data bus is used to wri te ...

Page 71: ...ration In the DMA mode a MEMRN a MEMWN a IORN and an IOWN signal are output signals When CPU control mode these signals are input signals 2 3 6 3 8 bit DMA Interna Memory Interna Memory Figure 2 3 18 shows the 8 bit DMA Internal memory Internal memory operation First the DMA controller stores memory data Next the DMA cont ro ller changes address signal and writes the stored data to the memory 2 3 ...

Page 72: ...0 iZlI I I I I I c PU G TCB Refer to the seetl0 for 110 de l ce aeee elrcult IXIQWN XIORN I I I l M J 11_Thl 19na1 _s low when the 1 0 addre 80H through 9FH are eleetad I I 11 I G rOB I H I I I Refer to the eet1on for 1 0 de l e leeess ci rcutt FIGURE 2 3 16 DHA CONTROL CIRCUIT I SETnNG OF PAGE REGISTER ...

Page 73: ...1llOd XAD 9 no1 s usec fo on 1nputr t 1n l 1_ I i I 10 GAATM21 OMA2 I 8237AD 0 DACKOI CPU GAATCK HRQ HLOA I I L ft t I HRO H DA In 0 OMAI ope t10n IIOdI j llMA2 1nh1b1ts output s 1 gools I elpt HRO 0 9nol FIGURE 2 3 17 DHA CONTROL CIRCUIT II INTERNAL MEMORY 8 BIT DHA GAATOB N I OPTJON SlOT To 1nter nl 1 RA AODRESS A8 S A15 o GAA1Ml o I O tl o I j o tl i ...

Page 74: ... 0 C l GAATCK GAATAB GAATRF 8237A 5 0 z l 0 tl 07 I tzj 00 0 z I I I I ICPU GAATCB GAATIO GAATDB To lnternal llAM Mll7 MOO 507 500 L5245 FIGURE 2 3 18 DHA CONTROL CIRCUIT 111 IRTERNAL MEMORY IRTERNAL MEMORY 8 BIT DHA s ...

Page 75: ...NSS AO 119ft 1 1I kapt o AEN I IADSTB GAATM AddNSS A8_A15 GAATRF DHA COBTROL CIRCUlT IV IRTEBNAL MEMORY 1 0 16 BIT DHA MDIS GAATDB 10 Inta a1 RAH GAATAB GAATCB MIlO r N011 0 IlOl1 00 AI SAn i WIe SAO SAI611 dll 9aMiad exc pt D lIAM refresh lIOde 1 0 lAI FIGURE 2 3 19 CPU GAATM OPTION StOT TC GAATCK SD15 OPTION StOT f SDD N I 01 I ...

Page 76: ...e by using jumper connectors 4 5 and J6 But t he seleetion is available onJ y for lOt lHz use TABLE 2 3 11 WAIT CYCLES DEVICE ID BE ACCESSED WAIT CYCLES IDTAL CYCLES 6MHzI 8MHz lOMHz tt tn o o tt o z 16 bit memory 16 bit bus operation DRAM System memory 00000 to 9FFFF M OEOOOO to OFFFFF FEOOOO to FFFFFF r o channel Other range 8 bit memory on r o channel 8 bit bus operation 8 bit memory on r o cha...

Page 77: ...5 4 B C A C B C B C B C A C A C B C A C A C Ignored 2 3 7 1 Insertion More Wait Cycle 1 2 1 2 3 4 N I hen you want to insert more wait cycles Please control the IOCHRDY 1 0 channel Ready signal When the IOCHRDY signal is high a wait cycle will be inserted 2 3 7 2 Zero Wait Cycle Request To insf rt no wait cycle a OWS signal is provided on the option slot This signal is low when active C H C o i o ...

Page 78: ...ADV GAATAB GAATCB GAATDB GAATRF GAATIO GAATMl GAATM 2 OPT ION 0 OWS SLOT d o i FIGDRE 2 3 20 lilien the low aethe OlIS 1911a1 1 t f tho OpUon lot tho alt eycll 1S not ln rtod No alt eycll READY SIGNAL CONTROL CIRCUIT ...

Page 79: ...delay function it is necessary to send a CDLY Command delay signal to the GAATCK The GAATRF outputs a CDLY signal when it detects the following mode listed in Table 2 3 13 automaticaly FIGURE 2 3 21 TIMING BETWEKN ADDRESS SIGNAL AND READ WRITE SIGNAL ADDRESS v SIGNAL TABLE 2 3 13 CONDITION OF TRE CDLY SIGNAL OU JPUT j trJ tJ I N I Jl w 1 2 3 CONDITION OF TRE CDLY SIGNAL OU JPUT 1NTA mode 1 0 read ...

Page 80: ... slgn ls mrcßY 1 INTA _ 2 IID d lID Wl lte 16 bit o e bit __ 3 d I Wl lte Onlye bit d l R f n Dlff n bet_n READY slgn 1 nd COItlAND DELAY slgn 1 READY CXlItWlD 1 tl C f o i o tl t Il o z I I 1 51 50 IoI 11l GAATIO GAATM 2 CXlItWlD DELAY slgn 1 TS TC TC Ts Sl 50 Bdl ISulp CIoIDLY _ 1 _ READy r GAATDB FIGDRE 2 3 22 COMKAND DELAY SIGNAL CONTROL CIRCUIT 5 ...

Page 81: ... date bus buffe regi ste of the Most r l8042 8742 thls signal go 8259 A 2 act1ve INT IRO 8254 OUTO IRI 8042 8742 P24 4 Yli JA 0 IR2 I IRJ TRJ 110 slot IR4 IR4 H IR5 IR5 00 IR6 IR6 H INTA IR IR 5 CAS2 CASI rN CASO H MASTER IClDE v J 146818 IRQ I lINTA Ii VD V I When the IHTA s1gnal 1s aeth thls s1gnal go 1 GAATIO NE f _IR1JI _ I Al S245 0217 EAItO t 002 lIUSf G TDB I HLOA H SDO MSTR H I others L GA...

Page 82: ...ing of the jumper connectors J4 JS J6 and J7 Functional description of each jumper connector is explained in CHAPTER 7 2 3 10 1 Available ROM Types You can install the following type of ROM chips TABLE 2 3 14 AVAILABLE ROM TYPES C o o C tz l H o 2 ROM TYPE RECOMKENDED ACCESS SPEED JUMP ER SEl TIRGS J4 J5 27128 2764 27256 200ns or more higher 200ns or more higher A C B C A C B C ...

Page 83: ...A16 OFoooo OFFFFF OEoooo OEFFFF FFoooo FFFFFF FEoooo FEFFFF OF8OOO OFFFFF OFoooo OF7FFF XAJ XA15 FF8000 FFFFFF FFoooo FF7FFF OE8OOO OEFFFF OEoooo OE7FFF FE8000 FEFFFF FEoooo FE7FFF ARENN REYN o GAATDB GAATAB GAATCB FIGDRE 2 3 24 f i AI6 OXA GATE LA CIl XAI CP 015 ROYN 00 CPU READY 10 50 N 5J N 5 50 m 16 TOGur B lOG T N I VI oll ...

Page 84: ...h the CPU executes a bus hold cycle The RFNO Refresh output signal is an important signal From this signal the GAATM1 makes a RAD and a RA1 signal RAS signal The GAATM2 controls the refresh address by using this RFNO signal And more this signal is used by the 8 bit binary counten as a count up signal Figure 2 3 25 shows the D RAM refresh control circuit operation tl H o Zi H i ...

Page 85: ... GAA T10 AlN 1 Por 2 B 1 0 reg1St r 61H bit GAATRF GAATOB GAATAB GAA TCB N L E RN GAAT 2 l5590 abil bln RSN I v 1115_ Counter Q G GWONI I I I CD C O 110 HRQ HLDA C PU GAATCK WE N I VI FIGURE 2 3 25 Ifmlrnj 10PTlON SLOT D RAM REFRESH CIRCUIT tl o o tl i ...

Page 86: ... the GAATM1 outputs a PCKN signal The GAATIO receives a PCKN signal and makes a NMI Non maskable interrupt signal Figure 2 3 26 and Figure 2 3 27 show the RAM parity check circuit operation Iod tn oP Zj o Iod tz l o 2i P04164 equivQ nt P04164 equivaient 01 01 MB81256 equivalent 01 MS81256 0 I qui Glent MPll GAATMI GAATRF CPU N J 00 llillQ GAATM2 M015 MOO FIGURE 2 3 26 RAH P ARlTY CHECK ClRCUIT DAT...

Page 87: ... CKN 00 811256 J P04164 0 0 equivOlent eQUivolent 1S r Ii DI 21 01 ko r L 00 rni bo 00 CPU GAATCB o OO 11256 IP04164 0 0 eQuivalet uivQlftlt GUTtO GAA TM2 lc NMl 811256 811464 or la or 2 N I Cu eQu volent qui vo e t r IN 03 f I 00 00 GAATDB 110 Raoi te I n 811256 811464 2 or or eQuivolent t eQuivolent N I VI Cl ...

Page 88: ...shows the speaker control N I 0 o GAATCK GAATAB GAATRF 8254 2 i _ GATEZ C KZ i IOUTZ EH CI o z l o t r i 2 CPU GAA TCB 8ltO 01 l O aeldreSl 61H Ti g UZ OIlIOFF contra I blt GAATDB 8ltl 01 1 0 addreSl 61H Speake OFF contra I bl t O OFF 1 0Il ede c cg lg rt Speike FIGURE 2 3 28 SPEAKER CONTROL CIRCUIT 5 ...

Page 89: ...042 receives keyboard data it sends an interrupt request signal from P24 pin P26 pin of 8042 outputs control signal of keyboard data transmission In detail Refer to section 2 2 2 3 14 2 RAM Size Reading The 8042 reads the condition of jumper connector J2 on the ANT RM board 2 3 14 3 Monitor Setting Reading The 8042 reads the condition of slide switch SW1 on the ANTA board 2 3 14 4 Disabling Keyboa...

Page 90: ...6 Address A20 Signal Control The 8042 outputs A20 control signal gate signal to GAATRF GAATRF controls A20 signal as below TABLE 2 3 15 A20 SIGNAL CONTROL BY GAATRF O A20G A20 0 1 0 1 1 1 0 0 DON CARE d 1 1 o Zj i ...

Page 91: ...l o l o tl i GAATMI GAATRF GAATAB GAATCK f1 RC CAZO_ AZOG_ r AMT RM bCICI cl JZ 0 AZO_ o r CPU GAATCB AZO JRAL AZO GAATlO GAATMZ YQ r Y I 8042 8742 GAATOB SWI r PI PI y y PU f PZ I TESTO PZ TESTl I P Zl I I ro tJi PZO I Pl1 Key Cylinde Swltch l KID CLK KID DATA N IJ ...

Page 92: ...OSC T C 2 IOWN IORN EOP J OACKO 1 2 3 5 5 7 SCLK I lOR MEMRN IOW MEMWN CLK OMAC2 SAO 19 lOl N I OACK 5 a SOO 15 PWGO IRQ J 4 5 5 7 9 10 11 12 14 15 Ml N f ol MEMR MEMW CPU GAATCB ORQS L IOCS1 lORN lOWN MEMCSI5 SA17 oLAI7 Z3 EOP SA MASTER 0 saHE GAATIO POWER GOOO LAI7 l IHTC SMEMW I IR3 SMEHR LA23 7 MEMRN 9 t I MEMWN 12 cgNOl1 1 NOIZ 15 NOQ saHEN GAATOB SOlS r RTC 145818l SOO I I es FIGDRE 2 3 30 1...

Page 93: ...ted in CHAPTER 7 Ir I es 2 SCSN 8 SIFO oQ_ B SIF 1t l_ GAATSP C A J6 Gi FIGURE 2 4 1 16450 CHIP SELEGT CIRCUIT BPS can be set DC to 56000 bps The 8250 and the 16450 are indentical in their functions however handling speed of the 16450 is higher than that of the 8250 2 4 1 2 Interrupt Signal Interrupt signal goes high whenever any one of the fo11owing interrupt types has an active high condition an...

Page 94: ...wo kinds of 1 0 addresses on the parallel Data control circuit They are selected by jumper pin J3 and J4 Setting of J3 and J4 are listed in CHAPTER 7 GAATSP PIFO PIFl C A J4 9 FIGURE 2 4 2 1 0 ADDRESS SKLECTION 2 4 2 2 Parallel Data Control Circuit Functions Parallel Data control circuit has the following six functions 1 Data output circuit 2 Output data read circuit 3 Printer control signal outpu...

Page 95: ...ER DATA REGISTER WRITE Output Data Read Circuit The output data for printer ean be read via LS244 loeated in the GMTSP I 0 0 1 007 S07 OLO OS 8r o f r I f soo f f 000 OE r _ f y Af Y L Af y S Ar y 2 Af y 4 Af 4 y A I L I oo J GAATSP FIGURE 2 4 4 OU1PUT DATA READ CIRCUIT Printer Control Signal Output Circuit GAAT5P bil 507 507 OIRE 0511 5LCT IN OINI INIT n r OATF AUTO FO Xl 500 500 05T8 5TR08E FIGU...

Page 96: ...ROBE 5LN INI ATF 5 TB 4 FIGURE 2 4 6 PRINTER CONTROL SIGNAL READ CIRCUIT Printer Status Read Circuit GAATSP S07 S03 S07 l t BSY S06 S I ACK 2 SOS 4 I EOP 4 S04 t Sl P S03 G t ERR I ADORESS I lJECOOER BUSV ACK PE SlCT ERROR FIGURE 2 4 7 PRINTER STATUS READ CIRCUIT Interrupt Signal Control Circuit ACK J10 B C ___ A OJRE I IRE bit JRS JR7 GAATSP FIGURE 2 4 8 IlITERRUPT SIGNAL CONTROL CIRCUIT 2 68 ...

Page 97: ...IVE SELECT 1 DRIVE SELECT 2 MOTOR ON DIRECTION STEP WRITE DATA WRITE GATE TRACK 00 WRITE PROTECT READ DATA SIDE SELECT READY GND FDl155C MD5501 2 MODE SELECT NOT USED DRIVE SELECT 3 INDEX DRIVE SELECT 0 DRIVE SELECT 1 DRIVE SELECT 2 MOTOR ON DIRECTION STEP WRITE DATA WRITE GATE TRACK 00 WRITE PROTECT READ DATA SIDE SELECT DISK CHANGE GND NOTE 1 2 3 SD 581L is used in the EQUITY II EPSON PC FD1l55C...

Page 98: ...and J1 Setting of J2 and J1 are listed in CHAPTER 7 2 4 3 2 Interrupt Signal and DHA Request Signal from FDC FOC 765 IH1 VQ I bit I ORQ OfF OQ OY 0ACii I CIJICU T ORa CAH a CAKH CR H Z T GM1FO KZ ORG CA IRQ FIGURE 2 4 10 INTERRlPT SIGNAL AND DHA REQUEST SIGNAL FROH FDC 2 4 3 3 FDD Control Signals MFM FM signal of FDC is not used MFM FM is se1ected by a software command Disk Change Signal V hen 1 0...

Page 99: ...ER 00 J 2 WOATA FWO WRT wo OATA PS1 PS1 PSO PSO FOO WE WE GAATFD FIGURE 2 4 11 FDD DATA WRITE CIRCUIT FDD register of the SPFG board can select PC AX mode and PC AT mode by jumper switch J2 In case of the pe XT mode CLK and WCLK output generated in the gate array GAATFD is fixed Note When jumper connectors J1 and J2 are set to 0 0 it is impossible to access the FDD register 2 71 ...

Page 100: ...ta transmission speed 1 SOOK bps mode 2 300K bps mode 3 2S0K bps mode These modes are selected by AO DO D1 WR and 3XVN signals REV A FDC 765 VFO 2 72 WINOOW WINOOW RAW RO RO OATA RO SYNC SYNC C AO 00 01 WR 3XVN WClK I 3XVN WClK GAATFD FIGDRE 2 4 12 FOD DATA READ CIRCUIT REAO OATA ...

Page 101: ...LK signal The VFO circuit will synchronize whether a weLK signal or RAWRD signal is selected by SYNC signal Whether the VFO circuit is synchronized vith lJCLK signal or RAWTD signal is selected by SYNC signal When 500Kbps or 250Kbps this signal becomes active VCO IC WINOOW o _f 1 1 2 EI f IIIlen JOO bps E2 this signal bacomes activa VCOFB 500KBPS I I I i 1250K 300K BPS FIGURE 2 4 13 VFO WINDOW CIR...

Page 102: ...E A DRIVE 8 FIGURE 2 4 14 FDD TERMINATOR FUNCTION FDD Special Signal Cable When changing setting of floppy disk drive number A or B it lS not necessary to change floppy disk drive jumper setting You can change the setting of floppy disk drive number by modification of the connections on the floppy disk drive signal cable i SPFG BOARD DRIVE A DRIVE B SPFG BOARD FIGURE 2 4 15 FDD CABLE SETTING 2 74 ...

Page 103: ...enerated at the host side drive B is selected If MT2 signal output is generated motor in drive B is turned on FIGDRE 2 4 16 DRIVE SELECT AND MOTOR ON SIGNAL SlPPLY CIRCUIT Always set the drive select jumper switch to DS1 Drive Select 1 OJGNO CHANGE GNOep I GNOm DSO 10 GNO 11 DSl 1 GNO 13 DS2 14 GNO MOTOR ON 15 116 GND I I I I DISK CHANGE IORlv 1 FIGURE 2 4 17 FDD SPECIAL SIGNAL CABLE 2 75 ...

Page 104: ...tting You can change the setting of the hard disk drive number by modifying the connections of the hard disk drive signal cable Remark Concerning hard disk drive s terminator they are not identical to the floppy disk drive When you install the second hard disk drive you must remove one terminator from drive number D HOST DRIVE C 5V t 220 ohm L c e TERMINATOR SW 330 ohm ON 7 7 I DRIVE D t o 5V 1 20...

Page 105: ...e selection is performed by software Key code output mode a AT mode Key code output mode b Keyboard unit Key code output mode c XT mode The EQUITY 111 EPSON pe AX system uses the key code output mode of the AT mode 2 5 1 Block Diagram The following diagrarn shows keyboard unit block diagram DRIVER LED CPU KEY MATRIX CLOCK DATA MULTIPLEXIER FIGURE 2 5 1 KEYBOARD UNlT BlOCK DIAGKAM 2 77 ...

Page 106: ...om the host to the keyboard At this mode the keyboard sends clock signal to synchronize between the keyboard operation 2nd the host side operation TABLE 2 5 1 INTERFACE CORTROL MODE CLOCK DATA FURcnON II L L H H H L L Keyboard can send Data to Host side Keyboard can t send Data to Host side Keyboard prepares receiving Data Keyboard starts inputting Data KEYBOARD HaST SIDE CLOCK CLOCK DATA DATA TAB...

Page 107: ...ecks the clock line during transmission of data and will stop transmission when it detects there is a 10w level signal 2 5 3 2 Data Keyboard transmission keyboard scan code command code reception code command code data This is also the transmission request signal from the host level signal is detected in the data line the keyboard is reception 2 5 3 3 Keyboard Data Output AT mode Once a 10w ready ...

Page 108: ...oard changes the signal in the data line to low level and receives one more bit the stop bit The low level signal of the 11th bit teIls the host that the data has been received 2 5 3 5 Data Transmission Method and Data Format TADLE 2 5 4 DATA TRANSMISSION ME l1IOD AND DATA FORMAT 1 Transmission method Synchronous serial Synchronous serial transmission transmission 2 Transmission rate 9600 BPS 9600...

Page 109: ...5 60 us Min Host data output ready time T6 5 us Min FIGURE 2 5 3 KEYßOARD DATA IWUT AT MODE T4 T2 f START 1 __D_0 0_l_ _0_2_ DATA CLOCK Tl T2 T3 T4 100 250 us 104 us 20 10 us Min 10 us Min Oata output possibility check time FIGURE 2 5 4 KEYBOARD DATA OU JPUT XT MODE 2 81 ...

Page 110: ...A CLOCK HEV A S6P 74LS125 equ valent FIGURH 2 5 5 IRTERFACE CIRCUIT 2 5 5 Connector P in Explanation DIN connector FIGURH 2 5 6 KEYBORAD CORRKCTOR PIK LOCATIOKS TABLE 2 5 5 KEYBOARD CONNECTOR P IN FUNCTION 2 82 PIK NOMBER 1 2 3 4 5 SIGNAL NAME Clock Data N C Ground 5V DC Ground ...

Page 111: ...ff FIGURE 2 5 7 STROKE CHARACTERISTlCS 2 5 6 2 Typematic Function A key scan code i8 transmitted as long as a key is depressed Transmission intervals for all keys except the F16 P ause key depend on the typematic rate delay command assignment When any of the other keys are pressed it enters a new typematic cycle Keyl Key2 Data 0 Tl T2 Tl FIGURE 2 5 8 TYPEMATlC FUHCTlON 2 83 ...

Page 112: ...even during an overrun Hmlever t they will be cancelled by a buffer clear command The overrun code is different between mode and mode below TABLE 2 5 7 OVERRUN CODES KEY CODE OU1PUT MODE AT mode XT mode 2 5 6 4 Power On Reset AT mode a b c FF 00 00 FF When the power is tUl ed on the keyboard logie performs a power on reset 1 Following the power on reset t a self test program is performed ROM check...

Page 113: ...gnal is detected 1 Key scan memory clear 2 Buffer FIFO clear 3 Self test program performed ROM sum check RAM check self test program self test program 4 Transmission of self test program end code A AlI FeH Operated correctly Operated abnormally scanning is stopped after transmission of the end code 2 5 6 6 Data Wait Function XT mode When the start bit is set the data line is checked by the keyboar...

Page 114: ...native operation does not take place when the control Gtrl key is pressed Typematic Out 1 I I I I I I Lock Key Data Out ONI I I Ctrl Key Indication J ON O N I __ FIGURE 2 5 9 BASIC OPERATION OF MODE IlIDICA l OR DISPLAY Special Operations For Germany and French By pressing the Gaps key Gaps Lock indicator becomes on light By pressing the shift key Gaps Lock indicator becomes off Not light Caps Key...

Page 115: ...1 MODE h MODE a General Other x x Keys A09 B20 AI2 EO x EO x Extension A D EI4 E16 EO x EO x Key 1 BI5 Extension E18 EO x EO x Key 2 Extension Fl4 EO x EO x Key 3 Shift BOO Bll x x Key Special FI6 Pause 8 bytes 6 bytes Key Make code is substituted by FO x 80 is added to make code x OR M TE 1 2 Note 1 Note 2 Make code When key is depressed Break code When key is released The x code indicates scan c...

Page 116: ...code transmission i The table below shows the key stroke conditions for transmission of extension left and right shift codes TABLE 2 5 10 KEY STROKE CONDITION N LOCK NOT N LOCK N LOCK 2 88 EXTENSION SHIFT SETTING Extension shift off code is transmitted when extension key l or extension key 2 is pressed after the shift key has been pressed In case of pressing extension key 2 same operation is perfo...

Page 117: ...e Extension Right EO 59 EO 36 Shift on code Extension Right Eü Fü 59 Eü B6 Shift off code iii Transmission sequence of left and right codes are as folIows TABLE 2 5 12 TRANSMISSION SEQUENCE OF LEFT ABO RIGBT CODES KEY CONDITION Extension Shift Setting TRANSMISSION SEQUENCE EXS x Extension Shift Release Hhen extension Shift setting key is OFF x EXS When other keys are ON EXS x Note x EXS Key data E...

Page 118: ... below are transmitted when the F14 Sys Rq key is pressed lhile the A01 left Alt the A09 right Alt and the AOa left Ctrl A12 right Ctrl key or the BOO Left shift and BII right shift keys 4 Key code output during typernatic operation All keys except the F16 pause key are typematic keys whose make codes are transmitted at specified intervals TABLE 2 5 14 TRANSMITTED CODE OF F14 Sys Rq KEY WIIEN AOO ...

Page 119: ...d repeatedly 4 The break code transmission keys in 2 and the typematic keys in 3 above are set during default and all keys can be set with the commands described below 2 5 7 2 Key Code Output XT Mode The Key code outputs are performed according to the same conditions that prevail in key code mode a during AT mode inc1uding shift function 2 5 8 COMMANDS AT mode 2 5 8 1 Commands From the Rost Side T...

Page 120: ...Default disable The keyboaed stops seanning and exeept that it waits for a eommand it behaves as during a set default command 5 Enable The keyboard aeknowledges to the host side with and ACK eommand and clears the output buffer Then starts seanning 6 Set typematic Rate Delay This command is made up of a 2 byte command and parameter The keyboard responds to the ACK command stops scanning and waits ...

Page 121: ... 0 1 0 24 0 1 0 0 1 0 6 0 0 0 0 1 1 21 8 1 0 0 1 1 5 5 0 0 1 0 0 20 0 1 0 1 C 0 5 0 0 0 1 0 1 18 5 1 0 1 0 1 4 6 0 0 1 1 0 17 1 1 0 1 1 0 4 3 0 0 1 1 1 16 0 1 0 1 1 1 4 0 0 1 0 0 0 15 0 1 1 0 0 0 3 7 0 1 0 0 1 13 3 1 1 0 0 1 3 3 0 1 0 1 0 12 0 1 1 0 1 0 3 0 0 1 0 1 1 10 9 1 1 0 1 1 2 7 0 1 1 0 0 10 0 1 1 1 0 0 2 5 0 1 1 0 1 9 2 1 1 1 0 1 2 3 0 1 1 1 0 8 6 1 1 1 1 0 2 1 0 1 1 1 1 8 0 1 1 1 1 1 2 0 ...

Page 122: ...ion Then keyboard responds to the option sets the indicator and starts scanning when proceeded as an Enable If it receives another command instead of the option the indicator condition remains unchanged and the keyboard stops this command operation Then proceeds the new command and starts scanning TABLE 2 5 17 OPTION REGISTER FüR KEYBOARD MSB LSB SCROLL LOCK INDICATOR NUMERIC LOCK INDICATOR CAPS L...

Page 123: ...key code mode option data 01 03 The keyboard is set to specified key code mode depending on the option data TABLE 2 5 19 K EY CODE MODE ON OPTION DATA OPTION DATA K EY CODE MODE 01 a 02 b 03 c 11 Typematic key set This command is made up of a eommand and an option Max 4 or 5 bytes The keyboard responds to this command with an ACK command stops scanning and responds to the option with an ACK comman...

Page 124: ...tting BREAK CODE TRANSMISSION Setting Cancel Setting Cancel REMARKS Applied for only key code mode c 2 5 8 2 Commands To Host Side These are commands transmitted to the host side by the keyboard TABLE 2 5 21 COMMANDS 1 0 l HE BOST SIDE COMMAND Resend ACK Overrun Break Code Prefix BAT Completion Echo Response Read Keyboard ID Read Key Code Hode Key Code Hode a FF Key Code Hode b c 00 DATA HEX FE FA...

Page 125: ...his command is transmitted in response to an equipment ID data read cornmand from the host side 8 Read key code mode This command transmits current keycode mode status in response to a key code mode read cornmand from the host side TABLE 2 5 22 KEY SCAN CODE LIST KEYNO MODE a MODE b MODE c KEY NO MODE a MODE b MODE c FOO 01 76 08 EI3 2 7D 6A 5D F02 3B 05 07 E14 EO 52 EO 70 67 F03 34 06 OF E15 EO 4...

Page 126: ...C07 24 3B 3B B15 EO 48 EO 75 63 C08 25 42 42 B17 4F 69 69 C09 26 4B 4B B18 50 72 72 C10 27 4C 4C B19 51 7A 7A Cll 28 52 52 B20 EO lC EO 5A 79 C12 IC 5A 5A B20 2 78 63 78 C12 1 2B 5D 53 AOO 1D 14 II C17 4B 6B 6B A01 38 II 19 C18 4C 73 73 A05 39 29 29 C19 4D 74 74 A09 EO 38 EO ll 39 BOO 2A 12 12 A12 BO 1D EO 14 58 BOO 1 56 61 13 A14 EO 4B EO 6B 61 BOl 2C 1A 1A A15 EO 50 EO 72 60 B02 2D 22 22 A16 EO ...

Page 127: ...Section Title CHAPTER 3 OPTIONS TAßlE OF CONTENTS Page ...

Page 128: ......

Page 129: ... 2 How to use the MFG Board 4 2 RESPONSE AND INFOR 1ATION FOR ERRORS 4 5 Outl ine e 4 5 POD Function s 4 5 Explanation of POD Functions 4 5 Specific Pattern in 34H to 3DH 4 6 Response and Information of Errors 4 6 LIST OF FIGURES Fi gu re Title Page 4 1 1 Connection of Service Tools 4 1 LIST OF TABLES Table 4 1 1 4 3 1 Title Page Service Tool Listing 4 1 Responses and Information for Errors 4 7 ...

Page 130: ......

Page 131: ...L LISTING TOOLS NO PART NO DESCRIP TrON ANT MAC BOARD B778601601 Expansion board for the main control board MFG BOARD B77860170I Bus status check board CABLE IIE207 B77860I80I Expansion for CN3 of the ATRPS unit CABLE IIE208 B77860200I Expansion for CN4 of the ATRPS unit CABLE IIE2I0 B77860200I Expansion for DCI of the ATRPS unit CABLE IIE2II B778602I0I Expansion for DC2 of the ATRPS unit CABLE II...

Page 132: ...PC AX The POD will start automatically and check internal circuits step by step automatically 3 When error is occurred the error message will appair on the monitor screen or LEDs of the MFG board The POD does not show good message when no error 4 Search the RESPONSE AND INFORMATION FOR ERRORS and find the corresponding probable cause yourself 4 2 2 How to Use the MFG Board 1 Function of the MFG bo...

Page 133: ...4 ON ON ON ON OFF ON ON ON A3 A2 Al AO ON ON ON ON VALUE OF ADDRESS BUS o 0 0 0 0 1 0 0 0 8 o 0 0 0 0 080H INSTANCE 2 In case of setting the DIP switch to 1 0 address l77H DIP SWITCH 8 7 SW2 6 5 4 3 2 1 4 SWl 3 2 1 CORRESPONDING ADDRESS All A10 A9 A8 A7 A6 A5 A4 A3 A2 Al AO SETTING OF THE DIP SW ON ON ON OFF ON OFF OFF OFF ON OFF OFF OFF VALUE OF ADDRESS BUS 0 0 0 1 1 o 1 1 7 1 o 1 1 7 1 l77H 4 3 ...

Page 134: ...of the computer system 4 Meaning of the LEDs When the LED Iight t corresponding data bus is high status MFG BOARD LED NO MEANING LED 1 DATA BUS BIT 7 LED 2 DATA BUS BIT 6 LED 3 DATA BUS BIT 5 LED 4 DATA BUS BIT 4 LED 5 DATA BUS BIT 3 LED 6 DATA BUS BIT 2 LED 7 DATA BUS BIT 1 LED 8 DATA BUS BIT 0 4 4 ...

Page 135: ...cific key is pressed 3 If a serious error occurs refer to function 1 POD displays an error message on the CRT screen in addition to 1 0 address 80H 4 In reference to a non fatal error function 2 POD skips the specific key input wait status 4 3 3 Explanation of the POD Functions 1 Checking system hardware serious error See the table 4 2 Responses and information for errors 2 Checking system hardwar...

Page 136: ... Ver 1 02 RTC error corresponds to an error other than 163 time and date not set RTC time error corresponds to 163 time and date not set CRT DIP switch setting error or controller error Keyboard error FDD error HDD error CMOS 3FH Bit 0 X287 setting error corresponds to 162 time system options not set Bit 1 Key locked status Others Reserved set to 1 4 3 4 Response and Information of Errors The tabl...

Page 137: ...E REGISTER CHECK An error occurred during DMa page register check operation RTC REGISTER CHECK Changing from protect mode to real mode check An error occurred during RTC C MOS RAM area OFH check operation Checking is performed by setting and verifying each bit sequentially RTC C MOS RAM OF H Shut down status byte TIMER COUNTER CHECK Refresh function An error occurred during timer counter 1 For 07H...

Page 138: ...d not be set to 1 r o port 61H Refresh detect bit Half of the refresh signal frequency is indicated by this bit DMA REGrSTER CHECK For OBH An error occurred during checking the DMA controller 1 register For OCH An error occurred du ring checking the DMA controller 2 register None None HALT HALT 11H RAM and error bit pattern Replace RAM RAM Base 64KB CHECK An error occurred during checking the base...

Page 139: ...n ISA is faulty When ANT RM circuit board unit number Y12620300000 is used If no error is detected during RAM check but an error is detected during parity check LED indicated error message as folIows 1 llR 1 second 2 OOR 1 second 3 OOR 1 second In this case the error bit pattern is not indicated Note An error message is also displayed on the CRT screen The faulty RAM is detemined as folIows 000000...

Page 140: ...is automatically cleared by the 8042 8742 internal probram Replace8042 8742 KEYBOARD CONTROLLER SELF CHECK The normal termination code 55H was not returned when the keyboard controller seIftest program was executed Note The keyboard controller seIftest differs from the keyboard unit seIftest Replace 8042 8742 DATA TRANSMISSION CHECK BETWEEN KEYBOARD CONOROLLER AND CPU The IBF bit in the 8042 8742 ...

Page 141: ...AAH is written in avobe 83 84H port byte mode Then written data is read and the written data is compared with the read data This error is indicated if the written data was not equal to the read data INTERRUP CONTROLLER AND INTERRUP T MASKING CHECK For 23H An error was detected in the interrupt mask register of the master interrupt controller Checking is done writing and verifying 00 and FF in the ...

Page 142: ...cted in timer controller counter O For 26H It is set so that interrupt occurs after 60usec from the start of counter This error is indicated if an interrupt does not occur during the 90usec from the start of counter For 27H It is set so that an interrupt occurs after 200usec from the start of counter This error is indicated if an interrupt occurs du ring the 150 usec from the start of counter TIME...

Page 143: ...ror is occured NMI circuit has problem Ref NMI occurs under one of the following conditions 1 A RAM parity check error occurs 2 An 1 0 channel error occurs 108 System board error lOS System board error HALT HALT 2CH 8042 8742 Replace 8042 8742 KEYBOARD CONTOLLER STATUS REGISTER CHECK The IBF bit in the 8042 8742 status register was not cleared even after a fixed time elapsed Checking is done in th...

Page 144: ...ess lines A19 to A23 are detemined as normal If value of address 000000 is not FFFFH address line A19 to A20 has problem HALT 38H Unfixed value RAM Replace RAM RAM SIZE CHECK One of the following errors was detected during the checking of the RAM size 1 Bad RAM 2 A parity error An error address and error bit pattern are displayed on the CRT screen 1 If a bad RAM is detected An error address and an...

Page 145: ...tern This is same as the one explained for 11H Please see Note in the item 11H 2 For a parity error Data is indicated on the CRT screen as foliows xxxxxx 0000 202 Memory address error Parity check 1 or 2 1 RAM parity error Internal circuit 2 1 0 channel parity error Extension Memory card xxxxxx Error address 0000 All zeros are displayed t I n 3AH Unfixed value ADDRESS LINE A16 TO A23 CHECK One of ...

Page 146: ...ess error Parity check 1 or 2 1 RAM parity error Internal circuit 2 1 0 channel parity error Extension Memory card 3EH Keyboard Unfixed unit or value 8042 8742 Replace the keyboard unit or 8042 8742 KEYBOARD CLOCK CHECK The TO bit indicating the clock sent from the keyboard of the test input port in 8042 8742 was not turned low 304 keyboard or System Unit error CONTINUE 3FH Keyboard Replace the un...

Page 147: ...revious section is not returned or the response indicates an error 303 CRT error or System unit error CONTINUE t I 42H DJP Unfixed switch value setting Set the DIP switch correctly CRT SLIDE SWITCH SETTING CHECK The slide for setting the monitor did not match with the mounted video card If 40l CRT error is displayed on the CRT screen t the monochrome monitor was set by the switch but the video car...

Page 148: ...tions not set 164 Memory size error CONTINUE CONTINUE 42H RTC Unfixed 146818 value Replace RTC 146818 TIME AND DATE CHECK This error is indicated if the RTC control register was read but processing did not enter update in progress status or updqte in progress status could not be cleared 163 Time Data CONTlNUE not set 43H FDD Unfixed SPFG value circuit board or WHDC circuit board 1 Replace FDD 2 Mo...

Page 149: ...E m 45 H Setting Unfixed error value P erf orm set t ing correctly MAX CYLINDER MAX HEAD MAX SECTOR 1790 Disk 0 READ CHECK error This error is indicated if the POD 1791 Disk 1 can not read the Max sector of the error Max track which is determined by CMOS CONTINUE ol l I t C 48H ROM CHIP Unfixed on 1 0 value slot Rep lace ROM chip 1 0 ROM CHECK xxxxO ROM When the POD detect a 1 0 ROM ID error the P...

Page 150: ...inutes 59 seconds 59 4CH Unfixed value The lock was in locked status Unlock the key LOCK STATUS CHECK The lock was in locked status 302 System CONTINUE unit keylock is locked None P ARITY ERROR CHECK When a parity error was detedted Parity check 1 HALT Entire memory is parity checked again or The address of memory where the Parity check 2 parity error was detected is indicated with a 5 digit hexad...

Page 151: ... p I N Pari ty check 1 80000 S S Segment A parity error occurred in the segment placed at address 80000 or later ...

Page 152: ......

Page 153: ...1 20 5 2 5 2 1 5 2 2 5 3 5 3 1 5 3 2 5 3 3 5 3 4 5 3 5 5 3 6 Title 1AIN UNIT DIASSEt1BLY AND ASSH1BLY Upper Case Removal Upper Case Rep 1acement Front Panel Removal Front Panel Replacement Power Supply Unit ATRPS Unit Removal Power Supply Unit ATRPS Unit Replacement Optional Circuit Board Removal Optional Circuit Board Replacement Disk Drive HDD or FDD Removal Disk Drive HDD or FDD Replacement ANT...

Page 154: ...rd Removal Replacement 5 4 Disk Drive Removal Replacement 5 5 ANT ro1 Circuit Board Removal Replacement 5 6 ANTA Circuit Board Removal Replacement 5 7 ANT t1T Circuit Board Removal Replacement 5 8 ANT LS Circuit Board Removal Replacement 5 9 Speaker Removal Replacement 5 10 Key Cylinder Unit Removal Replacement 5 11 Secondary side Circuit Board Removal Replacement 5 12 Fan Unit Removal Replacement...

Page 155: ...rom the rear 3 Slide the upper case forward 4 Remove the upper case by opening the side section 1 in the direction indicated by the arrows B FIGURE 5 1 1 5 1 2 Upper Case Replacement A lPPER CASE Rml VALlREPLACEMENT 1 Fit the upper case over the Iower case 2 Slide the upper case to the rear 3 Replace the four screws C at the back 5 Lock the upper case if required 5 1 ...

Page 156: ...l 1 Remove the upper case 2 Remove the four screws A to remove the front panel Al B FIGURE 5 1 2 FRORT PAREL REMOVAL RFPLACEMERT 5 1 4 Front Panel Replacement 1 Replace the front panel by attaching the four screws A 2 Replace the upper case 5 2 HEV A ...

Page 157: ...t D about 6 em towards the front to elear the hold down tabs and remove the unit FIGDRE 5 1 3 POWER SUPPLY UBIT REtIlVAL REPLACEMEBT 5 1 6 Power Supply Unit ATRPS UBIT Replacement 1 RepIaee the power suppIy unit by sliding it toward the rear over the hold down tabs on the Iower ease 2 Fasten the power suppIy unit with the four sere lS C 3 Replaee the two ANT MT Board conneetors B and the FDD and H...

Page 158: ...olds the board to the Iower case 4 Remove the board by firmIy grasping the edge at both ends and pulling directIy upwards Al F IGURE 5 1 4 OPTIONAL CIRCUIT BOARD REMOVALlREPLACEMENT 5 1 8 Optiona Circuit Board Rep acement 1 Insert the optional circuit board into the ANT MT Board connector slot B 2 Fasten the board with screw A 3 Replace the cable connections 4 Replace the upper ease 5 4 ...

Page 159: ...se B A FIGDRE 5 1 5 DISK DRIVE REMOVAL REPLACEMERT 5 1 10 DISK DRIVE HOD or FOD Replacement 1 Place the slider B at the left to mount the drive horizontally or at the bottom to mount the drive vertically and attach the drive to the lower case 2 Fasten the drive with the two screws A 3 Connect the signal and power supply cables to the drive 4 Replace the upper case Note 1 Arrange the signal and pow...

Page 160: ...ower ease 3 Remove the ANT R board by grasping the edge at both sides and pulling direetIy upwards A B FIGURE 5 1 6 ART RH CIRCUIT BOARD REHOVALlREPLACEMENT 5 1 12 ART RH Circuit Board Replacement 1 Insert the ANT RM board in the ANTA board eonnector slot C 2 Fasten the ANT R board to the IO ler ease w ith the sereu B 3 Replaee the upper ease 5 6 ...

Page 161: ...onnector G 7 Pull the ANTA board out all the way to remove it F H B El FIGURE 5 1 7 ANTA CIRCUIT BOARD REt VALlREPLACEMENT 5 1 14 Hain ANTA Cireuit Board Replacement 1 Hold the ANTA circuit board C level and slide it horizontally toward the real until about 8 cm of clearance remains 2 Replace the connector G on th ANTA board 3 Slide the ANTA board horizontally to firmly seat it into the ANT l1T bo...

Page 162: ...A 6 Remove the five serews C fastening the ANT MT board B to the lower ease and remove the ANT MT board C B FIGURE 5 1 8 ART MT CIRCUIT BOARD REKOVALlREPLACEMENT 5 1 16 ART MT Circuit Board Replacement 1 Replaee the ANT MT board and fasten with the five serews C 2 Connect the two eonnectors A 3 Replaee the ANTA board 4 Replaee the ANT r board 5 Replaee the optional eireuit boards 6 Replaee the upp...

Page 163: ...k switch cable C 6 Remove the screws F fastening the ANT LS circuit board E 7 Remove the ANT LS board G D F Al El C B FIGURE 5 1 9 ANT LS CIRCUIT BOARD REMOVAL REPLACEMENT 5 1 18 ANT LS Circuit Board Replacement 1 Replace the ANT LS board E and fasten with the screws F 2 Pass the cable for the connector A through the hole G toward the main ci rcuit board 3 Connect the connector A 4 Connect the con...

Page 164: ...rd 3 Remove the serew C fastening the speaker to the mounting board 4 Remove the speaker Cl Al FIGUBE 5 1 10 SPEAKER REMOVAL REPLACEMENT 5 1 20 Speaker Replacement 1 Replaee the speaker on the mounting board tdth the serew C 2 Conneet the speaker eable to the eonneetor A on the ANT LS board 3 Replaee the upper ease 5 10 REV A ...

Page 165: ...he case lock switch cable A 3 Remove the screws fastening the key cylinder unit mounting plate 4 Remove the key cylinder unit mounting plate Bl Al FIGURE 5 2 1 KEY CYLINDER UNIT REMOVALlREPLACEMENT 5 2 2 Key Cylinder Unit Replacement 1 Fasten the key cylinder rnounting plate with the screws 4 Connect the connector B to the ANT LS board 5 Replace the upper case 5 11 ...

Page 166: ...nect the fan connector E 4 Remove the cable clamp F in the following order 1 Hold the cable clamp F and rotate the clamp so that the cut section of clamp 1S mated with the cut section of the power supply case 2 Remove the cut section of the cable clamp 3 Remove the cable clamp 5 Remove the cables G along the cut section of the power supply case to remove the secondary side circuit board Bl Al 0 F ...

Page 167: ...d the cut section of the cable clamp so that it will not come off 2 Insert the thinner section of the cable clamp in the hole on the power supply case 3 Connect the connector E to the secondary side circuit board CD 4 Fasten the secondary side circuit board with the four screws C 5 Fasten the cover B with five screws A 5 13 ...

Page 168: ... the secondary side circuit board 2 Rernove the four screws A to rernove the fan unit A FIGURE 5 3 2 FAN UNIT REMOVALlREPLACEMENT 5 3 4 Fan Unit Replacement 1 Fasten the fan unit B with the four screws A 2 Replace the secondary side ci rcuit board 5 14 REV A ...

Page 169: ... outlet 5 Slide the primary side board horizontally to remove the board E A C FlGUKE 5 3 3 PRIHARY SIDE CIRCUIT BOARD REMOVAL RPPLACEKENT 5 3 6 Primary side Circuit Board Replacement 1 Replace the primary side circuit board by sliding in horizontally 2 Fasten the primary side board with the five screws C 3 Fasten the two cables connecting the AC out let to the primary side board with the screws E ...

Page 170: ......

Page 171: ...Section Title CHAPTER 6 ADJUSTMENT AHD MAINTENANCE TAßLE OF CONTENTS Page ...

Page 172: ......

Page 173: ... 7 8 7 10 7 12 7 15 7 16 7 18 7 21 7 24 7 26 Figure 7 1 1 7 1 2 7 1 3 Table 7 1 1 7 1 2 7 1 3 7 1 4 7 1 5 7 1 6 7 1 7 DIAGNOSTICS PROGRAf 1 7 28 LIST OF FIGURES Title Page Slide Switch Setting 7 1 Va1ume Adj ustment 7 1 Jumper Connectars 7 2 LIST OF TAßlES Title Page Hain ANTA Board Jumper Connections 7 2 Factory Settings Main ANTA Board 7 3 System Memory ANT RM Board Jumper Connetions 7 3 Factory...

Page 174: ...scription 7 9 7 2 5 GAATDB Pin Arrangement 7 10 7 2 6 GAATDB Pin Description 7 11 7 2 7 GAATCK Pin Arrangement 7 12 7 2 8 GAATCK Pin Description 7 13 7 2 9 GAAH12 Pin Description 7 15 7 2 10 GAATIO Pin Description 7 16 7 2 11 GAATM1 Pin Description 7 18 7 2 12 GAATRF Pin Description 7 21 7 2 13 GAATSP Pin Description 7 24 7 2 14 GAATFD Pin Description 7 26 ...

Page 175: ...or Factory setting COLOR Color Monitor CPU Speed 6 8 10 Select Switch 6 r filz 8 MHz Factory setting 10 MHz MONO COLOR MONITOR SELECT OFF ON 1 11 I I 1c J1 LLJ 6 8 10 CPU SPEED FIGURE 7 1 1 SLIDE SWITCH SETTINGS Volume Adjustment Turn clockwise to increase the volume Turn counter clockwise to decrease the volume VOLUME FIGURE 7 1 2 VOLUME ADJUSTMENT 7 1 ...

Page 176: ... 3 in Fig 7 1 3 FIGURE 1 3 JUMPER CONNEC l ORS Hain ANTA Board Jumper Connections TABLE 1 1 MAllf ANTA BOARD JUMPER CONNECnONS Jumper Number Function J6 J5 J4 J3 J2 Jl A C Set CPU clock mode 6 8 10 E C Inhibit A C A C Inhibit A C B C Input CPU clock as NPX clock 1 3 B C A C Input 8 MHz as NPX dock B C B C Inhibit A C 2 wait cycles for EPROM access B C 1 wait cycle for EPROM access A C A C 4 ait cy...

Page 177: ...C 16 bit device access System Memory ART RH TABLE 7 1 3 SYSTEM MEMORY ART RH BOARD JUMPER CONNECTIONS Jumper Number J7 J6 J5 J4 J3 J2 J1 Function A C A G A C 640KB Memory A C A C B C 512KB Memory A C B C A C A C B C B C 256KB Memory B C A C A C B C A C B C B C B C A C B C B C B C OOOKB disable all RAM A C A C 27128 A C B C B C A C B C B C 27256 EPROM size A C A C Select ROM pair 24 and 24B A C B C...

Page 178: ... 24A and 24B Hard Disk Controller WHDC TABLE 7 1 5 HOD CONTROLLER WHDC BOARD JUMPER CONNECTIONS Jumper Number J3 J2 J1 Function HEV A B C A C B C A C B C A C Select primary address sets Select secondary address sets Non latched status LED Latched status LED WAR mode WA2 mode Factory Settings WHDC Board TABLE 7 1 6 FACTORY SETTINGS WHDC BOARD 7 4 Jumper Number J1 J2 J3 Factory Setting f C B C B C F...

Page 179: ... 27F IRQ 5 A C B C A C Parallel I F on video adapter 3BC 3BF IRQ 7 B C B C Disable parallel I F A C A C A C Primary serial I F 3F8 3FF IRQ 4 B C A C B C Secondary serial I F 2F8 2FF IRQ 3 A C B C Disable serial I F B C B C Disable serial I F A C AT drive I F B C EQUITY 3 drive I F A C Standard configuration B C Test mode of VCO Factory Settings SPFG Board TABLE 7 1 8 FACTORY SETTIRGS SPFG BOARD Ju...

Page 180: ...XA15 LSAO I 8 57 T DXA XAZ Tri 9 56 Tri XA14 XA3 Tri 10 55 Tri XA13 SAO Tri 11 54 Tri XA12 SA1 Tri 12 53 Tri SA16 SA2 Tri 13 52 Tri SA15 SA3 Tri 14 51 Tri SA14 SM Tri 15 50 Tri SAl3 GNDA 16 49 GNDB GNDB 17 48 GNDA SAS Tri 18 47 Tri SA12 SA6 Tri 19 46 Tri SAH SA7 Tri 20 45 Tri SA10 SA8 Tri 21 44 Tri SA9 XA4 Tri 22 43 Tri XAll XAS Tri 23 42 Tri XA10 XA6 Tri 24 41 Tri XA9 OP N I 25 40 I R590N XA7 Tri...

Page 181: ...System address bus Internal address bus Address latch enable A16 1 are latched by ALE Enable control of latched address A16 1 When low LSAO and latched A16 1 are enabled Direction control of internal address bus XA16 0 buffer When high XA16 0 are driven by SA16 0 and when low SA16 0 are driven by XA16 0 Clock of refresh counter Refresh counter increments at C590 rising edge Outpu t enable of refre...

Page 182: ...I I I I I I I I Tri O H Z Tri Tri Tri Tri Tri Tri Tri Tri Tri Tri Tri Tri Tri Tri Tri 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 I o I I o I I o I I Tri Tri Tri Tri O H Z O H Z O H Z O H Z O H Z Tri Tri Tri Tri Vcc Vi VO NRI2 NDl1 NRO NDIZ OOll 000 DXR GSRWN I...

Page 183: ...0 read signal Internal memory write signal Internal memory read signal System memory write signal 8 bit connector System memory read signal 8 bit connector Direction control of CPU address bus A23 17 buffer When high LA23 17 are driven by A23 17 And when low A23 17 are driven by LA23 17 Enable control of address bus SAI9 17 buffer When low SA19 17 are driven by AI9 17 Address latch enable A19 17 a...

Page 184: ...i 4 61 Tri Dl3 MDO Tri 5 60 Tri D12 MD1 Tri 6 59 Tri MD15 DMD I 7 58 I CBA GMDHN I 8 57 I SBA GMDLN I 9 56 Tri MD14 MD2 Tri 10 55 Tri 1Dl3 MD3 Tri 11 54 Tri MD12 SDO Tri 12 53 Tri SD15 SD1 Tri 13 52 Tri SD14 SD2 Tri 14 51 Tri SDl3 SD3 Tri 15 50 Tri SD12 GNDA 16 49 GNDB GNDB 17 48 GNDA SD4 Tri 18 47 Tri SDll SD5 Tri 19 46 Tri SD10 SD6 Tri 20 45 Tri SD9 SD7 Tri 21 44 Tri SD8 MD4 Tri 22 43 Tri MD11 M...

Page 185: ...ched or un latched data When high latched data are selected SBA is used in conjunction with CBA signal Direction control of Memory data bus HD15 0 buffer When high Memory data is read Enable control of Hemory data high byte MD15 8 buffer When low it enables high byte GMDEN is used in conjunction with D ID signal Enable control of Hemory data low byte MD7 0 buffer When low it enables low byte GHDLN...

Page 186: ... C48H Al I 3 62 I COFF RSWN I 4 61 I CDLY RSWP I 5 60 I CSPDO PWGD I 6 59 I CSPD1 NC 7 58 NC NC 8 57 NC NC 9 56 0 RSN ENAS 0 10 55 0 C1M DTR 0 11 54 0 EMEMR ACKN 0 12 53 0 DEN EALE 0 13 52 0 BALE RSDV 0 14 51 0 AEN CLKO 0 15 50 0 SCLK GNDA 16 49 GNDB GNDB 17 48 GNDA MEHR O lI Z 18 47 0 OSC MEMW O H Z 19 46 O H Z lOR ALE 0 20 45 O lI Z IOW lNTA O H Z 21 44 0 PCLKP DCLK 0 22 43 0 PCLKN RDY 0 23 42 0...

Page 187: ...LKO 12 MHz 16 MHz 20 HHz 24 MHz CLKl 12 MHz 16 MHz 20 MHz 24 MHz DCLK 3 MHz 4 MHz 5 MHz 6 MHz pweD RSWN RSWP RSN RSDV AREN ARDY SRDY RDY MIO SI SO I I I o o I I I o I I I 6 4 5 56 14 35 36 37 23 28 29 30 Power good When low it indidates that power is not good and reset signals RSN RSDV RSCPU are activated Reset switch activation signal RSWN becomes low Reset switch activation signal RSWP becomes l...

Page 188: ...tput indicates that a write bus cycle is being performed Hemory read command Hemory write command 1 0 read command 1 0 write command Interrrupt acknowledge Early memory read signal Early address latch enable Buffered address latch enable Haster A processor or DHA controller on the 1 0 channel may pull this signal low Acknowledge l Then low mtA controller or refresh controller has control of the ad...

Page 189: ...rite signal Early memory read signal Internal memory write signal Refresb signal 40 ns delayed signal from RAS 80 ns delayed signal from RAS 160 ns delayed signal from RAS 200 ns delayed signal from RAS RA1 signal is used to generate RAS1 signal RAO signal is used to generate RASO signal CAR signal is used to generate CASH signal CAL signal is used to generate CASL signal Row address strobe for DR...

Page 190: ...CK2 D acknowledge 2 DACKO D acknowledge O DACK4 This signal is output Refresh signal D acknowledge ACKN is active when DMA or refresh cycle is being performed DHAC N02 16 bit D controller address strobe signal DMAC N01 8 bit DMA controller address strobe signal Address enable signal of D C N02 Address enable signal of DMAC N01 AE02 is active when D C N02 has control of the system AE01 is active wh...

Page 191: ...ontroller 8042 Write signal of real time clock HD146818 Read signal of RTC HD146818 ALE signal of RTC HD146818 NP 80287 reset signal Chip select w 80287 CPU 80286 busy signal Interrupt request 13 Direction control of 8 bit internal data bus XD7 0 buffer Non maskable interrupt request Output signal for speaker Time r CH2 gate This signal is connected to channel 2 gate input of timer LSI 8254 Enable...

Page 192: ...F FEOOOO FE7FFF ALE I 15 HI1 A I 16 XMRN I 14 XBHE I 18 XAO I 19 JRAH J 60 JRAL I 59 JEFN I 56 JEO JROM J1MN 7 18 I I I 57 55 28 Address latch enable Hold acknowledge Internal memory read signal Internal bus high enable signal Internal address bus o Enable control of RAM from 080000H to 09FFFFH Enable control of RAM from 040000H to 07FFFFH RAM address select When low t RAM address is assigned from...

Page 193: ...gnal is used to generate CASH signal in GAATM2 CAL signal is used to generate CASL signal in GAATM2 Row address strobe for DRAM When GAATM1 1s used in memory expansion card This signal is not used in EQUITY 111 EPSON PC AX RAS2 Row address strobe for DRAM When GAATM1 is used in memory expansion card This signal is not used in EQUITY 111 EPSON PC AX Direction control of memory data bus buffer Dynam...

Page 194: ... HEV A Legend I o O H Z Input Pin Output Pin Output High impedance Pin no connection high or open low 20 In EQUITY 111 EPSON pe AX the following INPUT JEFN JEO JROM JIMN JKN RA23 D40 EPR2 OUTPUT RS3N RS2N MA9 ERON signals are not used ...

Page 195: ...led by WS1 CSPD WS1 Wait states 0 10 MHz 0 2 0 10 HHz 1 1 1 6 or 8 MHz 1 don t care WS2 I 39 WaU states control of 16 bit memory devices on the option card which activates MEMCS16 signal WS3 I 38 CSPD VS3 WS2 Wait states 0 10 mz 0 0 4 0 10 MHz 0 1 3 0 10 MHz 1 0 2 0 10 MHz 1 1 1 1 6 or 8 MHz 1 don t care AO ALE MEMR MEMW IOR IOW INTA CSRA CSRO M16 I 44 I 11 I 7 I 8 I 9 I 10 I 12 I 48 I 47 I 17 CPU...

Page 196: ... converted address O DNA channel 1 8 bit DMA address enahle D ffi channel 2 16 bit D adress enable mffi enable channel 1 and channel 2 Internal address bus O Bus high enable XBHE input output output XAO o AEN1 AEN2 XAO 1 1 input o 1 input 1 0 0 output Data bus enable Data transmit ot receive lIhen high data is transmitted from CPU to memory or 1 0 Enable control of CPU data hus low byte buffer in ...

Page 197: ...MA clock cyc1e from RFNI signal Refresh signal which is delayed by two DMA clock cycles from RFNI signal D memory read signal Internal 1 0 read signal D ready signal Internal memory read signal CPU address bus 20 A20 signal of CPU is connected to this pin Gate signal of A20 P21 signal of 8042 one chip CPU is connected to this pin System address bus 20 CA20 o 1 A20G 1 1 o A20 o 1 o don t care CLK S...

Page 198: ...ddress enable This signal becornes high when DMA cycle is being executed Reset Address select pin for parallel port Address select pin for parallel port PIFI 1 1 o o PIFO 1 o 1 o parallel port address 378 379 37A 278 279 27A 3BC 3BD 3BE disable SIFI SIFO I I 18 19 Address select pin for serial port Address select pin for serial port SIFI 1 1 o o SIFO 1 o 1 o serial port address 3F8 _ 3FF 2F8 2FF d...

Page 199: ...obe pulse Printer busy Acknowledge End of paper Printer select Printer error Interrupt request IRQ becomes active when ACK signal becomes low and interrupt request is enabled Interrupt request enable Acknowledge Chip select signal of serial port Direction control of data buffer This signal is active while serial port or parallel port are being read Legend I o Tri 0 11 2 Input P in Output P in Tri ...

Page 200: ...ddress select pin for FDC Address select pin for FDC FDIl FDIO FDC address AT XT 1 1 3FO 3F7 AT portI 1 0 370 377 AT port2 0 1 3FO 3F7 XT 0 0 disable When FDll FDIO 0 1 Floppy control register can not be accessed MOT2 MOTI DS2 DSI FRES RlvC 3X7N 3XVN FCSN BDIR 7 26 o o o o o o o o o o 30 29 25 24 49 23 32 47 44 59 Motor enable 2 DRIVE B Motor enable 1 DRIVE A Drive select 2 DRIVE B Drive select 1 ...

Page 201: ...output to 765 D request input from 765 D request output to 8237 Write data input from 765 Write enable input from 765 Peak shift input from 765 Peak shift input from 765 Write data output to FDD 48 MHz clock input Test pin Mini Standard for SED9420 16 9 6 MHz clock output for SED9420 FDC dock 8 4 8 4 rnz FDC write clock IM 600K 500K Hz Interrupt request of FDC input frorn 765 VFO synchronize input...

Page 202: ... 7 46 5 Color Graphics Adapter and CRT Check 7 52 6 Floppy Disk Drives and Controller Check 7 64 7 Math Coprocessor 80287 Check 7 70 9 Parallel Port Printer Interface Check 7 75 11 Serial Port RS 232C Check 7 78 12 Alternate Serial Port Check 7 82 14 Dot matrix Printer Check 7 83 17 Hard Disk Drives and Controller Check 7 85 21 Alternate Parallel Port Check 7 90 7 28 REV A ...

Page 203: ...roller check 9 80286 instruction check 10 146818 CMOS checksum and battery check 11 8259 Interrupt Controller check 12 8254 Timer Counter speed check 13 80286 protect mode check When the system board check is started the program displays following message I I I I SYSTEM BOARD CHECK I I I I The remainder of this section describes the procedures for each checking operation 1 80286 Processor Check Th...

Page 204: ...essage is identical to that of Item a 2 146818 CMOS Shutdown Byte Check The 146818 CMOS shutdown byte check performs a WRlTE READ check on the shutdown byte of the 146818 CMOS a The shutdown byte of offset 8fh of the CMOS is selected 01 is written and read and the value is checked The program displays an error message if the result does not match the initial value I I I I Error code 110 146818 CMO...

Page 205: ... Count 0 of the 8254 Timer Counter is 1atched and the count va1ue is checked Next acheck is repeated1y performed to confirm that all 16 bits have the va1ue of 1 The program displays an error message if any bit of the count va1ue of 1 cannot be read I I I I Error code 103 8254 TIMER COUNTER REGISTER ERROR l 1 I I I 5 8237 DMA Controller Check The 8237 DMA Controller check performs a WRITE READ chec...

Page 206: ...tect bit of Port No 61h and checks if its status makes a change The program displyas an error message if the status does not change 1 I I I Error code 105 8237 DMA REFRESH ERROR l I I I 1 8 8042 Keyboard Controller Check The 8042 Keyboard Controller check performs a check on the operating status of the Keyboard Controller a The status of the Keyboard Controller is repeatedly checked and the progra...

Page 207: ...The mode of the Keyboard Controller is reset to the following modes and this operation is terminated PC Compatible Mode Disable Keyboard Inhibit Override System flag Enable Output Buffer Full Interrupt 9 80826 Instruction Check The 80826 Instruction check performs a WRITE READ test on the System Table Registers IDTR and GDTR as weIl as a SET RESET test on the direction flag and interrupt enable fl...

Page 208: ...ery status is read to check if the battery is all right If not the program displys following error message I I I I Error code 111 146818 CMOS BATTERY ERROR I I I I b The CMOS shutdown byte is read to check if it is in Shutdown OK status If so this operation is terminated here if not execution proceeds to the checking of the checksum c The total sum of the data from CMOS offset 90h to Oadh is calcu...

Page 209: ...rocessing routine of 8259A is set to the special setting only the Count 0 output of the timer is placed into the interrupt enable status and the Count 0 value is checked a Starting with a Count value of 50 it is checked whether an interrupt occurs during 3memoryrefresh intervals The program displays an error message if no interrupt occurs I I I I Error code 104 8254 TIMER COUNTER ERROR I I I I b S...

Page 210: ...e A SET RESET check is performed on DF Direction flag and the program displays an error message if the set status and the DF flag of the CPU do not match The error message is identical to that of Item a f A boundary check is performed using the BOUND instruction then the absence of an out of boundary interrupt INT 5 is confirmed by checking the data within boundaries and the occurrence of an out o...

Page 211: ...escribed va1ue The error message is identica1 to that of Item a k The operation of the LSL instruction is checked The segment limit is loaded using the LSL instruction and is checked for being the prescribed va1ue The program displays an error message if the segment limit cannot be read or if it is not the prescribed va1ue The error message is identica1 to that of Item a 1 A WRITE check is perform...

Page 212: ...zzzzzz is either PARITY in case of a parity error or MEMORY in case ofa VERIFY error c Using Oaa55h as the test data acheck identical to that of Item b is performed d Using 010Ih as the test data acheck identical to that of Item b is performed e The test data 5555h and Oaaaah is written sequentially to the entire 64 KB area then a parity check is performed Next the test data is read and a VERIFY c...

Page 213: ...B Check of 20000h 2FFFFh a The contents of 20000h 2FFFFh are evacuated to 30000h 3FFFFh b to f A RAM check identical to that of Item 1 is performed g If the check of the 64 KB block is normally terminated the contents of 30000h 3FFFFh are re written to 20000h 2FFFFh h Next a message indicating the completion of the third 64 KB block check is displayed on the screen I I I I 000192 KB OK I I I I 4 6...

Page 214: ...h time a 64 KB check is completed the program displays following message I I I I XXXXXX KB OK I I I I The XXXXXX represents the total size of the checked memory block NOTE The base memorysize is checkedusing int 12h The expansion memory size is checked by reading CMOS offset 30h and 31h In case an expanded memory is installed the memory check is performed in protect mode of 80286 7 40 ...

Page 215: ...r code 301 l 8042 ERROR I I I I b The self test command is output to the keyboard The program displays an error message if the Normal Termination code is not returned I I I I Error code 301 8042 ERROR I I I I c The interface test command is output to the keyboard The program displays an error message if the Normal Termination code is not returned I I I I Error code 301 KEYBOARD ERROR I I I I d The...

Page 216: ... N is input the keyboard lock check is not performed b When the keyboard lock check is begun the following message is displayed so insert the key into the front panel and turn it to lock the keyboard I I I I Lock the keyboard using the front panel key I I I I The program displays an error message if the keyboard is not locked within the prescribed time I I I I l Error code 303 KEYBOARD LOCKING ERR...

Page 217: ... 101 or 102 keys by its response I Response I Keyboard Type only ACK I Old type 89 keys ACK ABh 41h I New type 101 or 102 keys The keyboard layout corresponding to the judged keyboard type is displayed By pressing an arbitrary key the character corresponding to the pressed key top will be displayed on the screen When y and ENTER is input the check is normally terminated If N and ENTER is input in ...

Page 218: ...directly read then the corresponding character is displayed a Layout of old type keyboard KEYBOARD CHECK Press Y followed by ENTER to exit Press N followed by ENTER if screen andkeyboard do not match b Layout of new type lOl key keyboard KEYBOARD CHECK Press Y followed by ENTER to exit Press N followed by ENTER if screen andkeyboard do not match 7 44 HEV A ...

Page 219: ...REV A DIAGRAMS AN REFERENCE MATERIALS c Layout of new type 102 key keyboard KEYBOARD CHECK Press Y followed by ENTER to exit Press N followed by ENTER if screen andkeyboard do not match 7 45 ...

Page 220: ... is performed The remainder of this section describes each of the checking procedures 1 Monochrome Adapter Check When the monochrome adapter check is selected the program displays following message I I I I MONOCHROME ADAP TER CHECK I I I I a A WRlTE READ check is performed on the VRAM area used for the monochrome display i The Video Enable signal of the monochrome monitor is set to OFF Next the te...

Page 221: ...y OOh is written to the entire VRAM area b Black White mode check of CRT status port The Video Enable signal of the monochrome monitor is set to ON status then the program displays following message I I I I MONOCHROME ADAPTER CHECK I I I I Next Offh is written to the latter half of the VRAM area B07DOH BOFAOH for the monochrome display and the CRT status port of 6845 is checked A Black White Video...

Page 222: ...es that can be displayed are shown on the monochrome display using characters ATTRIBUTE CHECK I I I I I I I I I Confirm whether each attribute is accurately displayed then input the answer If N is input the program displays an errormessage I I I I Error code 403 ATTRIBUTE ERROR I I I I 3 Character Set Check When the character set check is selected the entire character set from OOh to Offh is displ...

Page 223: ... display correct Y N 1f N is input an error message is displayed I I I I Error code 404 i i CHARACTER SET ERROR I I I I 4 Video Check When the video check is selected the following screen is initially displayed with a high intensity foreground color and a black background color 7 49 ...

Page 224: ...RENCE MATERIALS BLACK When any key is pressed the following screen is displayed with a black foreground color and a high intensity background color INTENSIFIED WHITE Pressing any key terminates this operation 7 50 HEV A ...

Page 225: ...sync check is selected the following screen is displayed Check this screen for any discrepancies in the synchronization of all lines 6 Run All Above Checks When Run all above checks is selected the checks described in Items 1 to 5 are consecutively executed 7 51 ...

Page 226: ...n case of test multiple times only the color graphics adapter check is performed The remainder of this section describes each of the checking procedures 1 Color Graphics Adapter Check When the color graphics adapter check is selected the program displays following message I I I I COLOR ADAP TER CHECK I I I I At this point a WRITE READ check is performed on the VRAM area used for color graphics a T...

Page 227: ...ismatch YY represents the written data and ZZ represents the read data b Next using the test data SSh an identical check is performed c Next using the test data Oaah an identical check is performed d Next using the test data Offh an identical check is performed Lastly OOh is written to the entire VRAM area the Video Enable signal is set to ON and this check is terminated 7 53 ...

Page 228: ... CYAN LIGHT RED LIGHT MAGENTA YELLO 1 WHITE High intensity Is the display correct Y N Confirm whether each attribute is accurately displayed then input the result The display has returned to the 80 x 25 character mode If N is input the program displays an error message I I I I Error code 503 ATTRIBUTE ERROR I I I I 3 Character Set Check When the character set check is selected the entire character...

Page 229: ...y correct Y N 1f N is input the program displays an error message I I I I Error code 504 CHARACTER SET ERROR I I I I 4 40 Column Character Set Check When the 40 column character set check is selected the entire character set from OOh to Offh is displayed on the screen in 40 column mode 7 55 ...

Page 230: ...I I I I I I I I I I 1f N is input the program displays an error message I I I I Error code 505 40 COLUMN CHARACTER SET ERROR I I I I 5 320 x 200 Graphics Mode Check When the 320 x 200 graphics mode check is selected the following image pattern is displayed on the screen This screen has been created by writing directly to VRAM Color setting 0 7 56 REV A ...

Page 231: ...EN I I I I I I I I I I I I I I I I I I I I BROWN CYAN 1s the display correct Y N I I I I I I I I I Confirm whether the pattern is accurately displayed then input the answer 1f N is input the program displays an error message I I I I Error code 506 320X200 GRAPHICS MODE ERROR I I I I 7 57 ...

Page 232: ...splay correct Y N I I I I I I Confirm whether the pattern is accurately displayed then input the answer 1f N is input the program displays an error message I I I I Error code 506 320X200 GRAPH1CS MODE ERROR I I I I 6 640 x 200 Graphics Mode Check When the 640 x 200 graphics mode check is selected the following image pattern is displayed on the screen This screen has been created by writing directl...

Page 233: ...led Confirm whether the pattern is accurately displayed t then input the answer 1f N is input t the program displays an error message I I I I Error code 507 l 640X200 GRAPH1CS MODE ERROR I I I I 7 Screen Page Check When the screen page check is selected t the characters 0 7 are respectively written to Pages 0 7 t then the screen paging according to the changing of pages is checked 7 59 ...

Page 234: ...he numeral corresponding to each page no is displayed After completing the check up to Page 7 confirm whether the screen paging was accurately displayed then input the answer SCREEN P AG1NG CHECK XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX...

Page 235: ...r Y to start light pen check l Enter N to return to the menu I I I I Next a white block is displayed on the the screen so press the light pen on the center of each block The address that is read from light pen is checked c i l b i a PLACE LIGHT PEN ON CENTER OF WHITE BLOCK Check the three blocks in the order of a b c The program displays an error message if the position where the block is displaye...

Page 236: ...Light cyan 13 Light red 14 Light magenta 15 Yellow 16 White high intensity After all of the background colors are displayed confirm whether they have been accurately displayed then input the answer I I I I Is the display correct Y N I I I I If N is input the program displays an error message I I I I Error code 510 l COLOR VIDEO ERROR I I I I 10 Sync Check When the sync check is selected the follow...

Page 237: ...HEV A DIAGRAMS AN REFERENCE MATERIALS I I I I I I 11 Run All Above Checks When Run all above checks is selected the checks described in Items 1 to 10 are consecutively executed 7 63 ...

Page 238: ...ly performed I I I I 1 Sequencial seek check 2 Random seek check 3 Write read check I I I I The remainder of this section describes each of the checking procedures 1 Sequential Seek Check Initially the number of floppy disk drives installedis checked by using Equipment Determination int 11h The program displays following message if two drives are installed so input the name of the drive to be chec...

Page 239: ...PPY DISK DRIVE S AND CONTROLLER CHECK Error code 601 FLOPPY DISK CONTROLLER ERROR I I I I The program displays an errormessage also when the seek operation of the FDC after performing head seek is not normally terminated FLOPPY DISK DRIVE S AND CONTROLLER CHECK Error code 602 SEQUENTIAL SEEK ERROR TRACK xx SIDE Y xx represents the error cylinder number and y representsthe error head number 2 Rando...

Page 240: ...d by writing and reading Head Nos 0 and 1 alternately to and from for all sectors of each cylinder from the innermost cylinder to the outermost cylinder 0 The check data is 6db6h I I I 1 WRITE READ CHECK I I I I Current track is xx I I I 1 The xx represents the number of the checked cylinder If an error is detected during the writing or reading of data the program displays following message FLOPPY...

Page 241: ...18 second and correcting by adding the number of the final Timer Count value Finally the program displays the revolution speed in rpm revolution per minutes expression 60 times interrupt count 18 sec times 60 sec The disk rotation speed should be more than xxx x rpm and less than yyy y rpm The disk rotation speed is now zzz z rpm Press any key to return to the menu xxx x represents the lower limit...

Page 242: ...m displays following message allowing you to return to the menu Drive X is no change line available DISK CHANGE is not allowed with this drive Press ENTER to return to the menu The X represents the drive name of the specified floppy disk If the drive is change line available the program displays following message then remove the disk from the drive I I I I Remove the disk from drive X I I I I The ...

Page 243: ... within the prescribed time the program displays following error message I I I I Error code 607 I DISK CHANGE CHECK INSERT ERROR I I I I REMARKS The disk change check reads the Digital Input Register of the FDC then checks the disk change flag of Bit 7 6 Run All Above Checks When Run all above checks is selected the checks described in Items 1 through 5 are consecutively executed 7 69 ...

Page 244: ...I I I I Error code 701 COPROCESSOR NOT INSTALLED I I I I b Check by Initialization The Initialize instruction finit is output to the coprocessor then the status word of the coprocessor is read fstsw to check the installation status If all error bits are not read as 0 the program displays following error message I I I I Error code 701 COPROCESSOR NOT INSTALLED I I I I 2 Initialization Check of Copr...

Page 245: ...VALID OPERATION MASK ERROR I I I I 4 Invalid Operation Mask Check after Clearing of Exceptional Bits All exceptional bits are cleared fclex then processing identical to that of Item 3 is performed At this time if the IR bit of the status word of the coprocessor is 1 the program displays following error message I I I I Error code 703 COPROCESSOR INVALID OPERATION MASK ERROR I I I I 5 ST Field Check...

Page 246: ...processor is 1 the program displays following error message I I I I Error code 706 COPROCESSOR ZERO DIVIDE MASK ERROR I I I I 8 Exceptional Data Addition Check The data items from Item 7 that resulted in zero division are added together At this time if the IR Interrupt Request bit of the status word of the coprocessor is 1 the program displays following error message I I I I Error code 707 COPROCE...

Page 247: ...I 11 Invalid Operation Mask Check 2 All exceptional interrupts of the coprocessor are masked then 0 is di vided by 0 to generate an invalid operation exception At this time if the IR Interrupt Request bit of the status word of the coprocessor is 1 the program displays following error message I I I I Error code 703 COPROCESSOR INVALID OPERATION MASK ERROR I I I I 12 Exceptional Data Comparison Chec...

Page 248: ...Addition subtraction multiplication division and the square root operation are performed then the precision is checked The program displays an error message if the mathematic result is incorrect I I I I Error code 710 COPROCESSOR PRECISION ERROR I I I 7 74 REV A ...

Page 249: ...Select Input 17 11 Busy Output signal Input signal After attaching the loop back connector to the parallel port issue the instruction to start the check PARALLEL PORT CHECK Attach loop back connector to parallel port Enter Y to start this check when connector is attached or Enter N to return to the menu The procedures for checking the parallel port are as folIows 1 WRITE READ Check of Data Output ...

Page 250: ...e control port is as folIows Bit no PIN no Signal Name o 1 Strobe 1 14 Auto Feed 2 16 Ietialize Printer 3 17 Select Input l 4 IRQ Enable 5 not use l 6 not use 7 not use If an unmatching bit is detected after performing the comparison the corresponding pin number is displayed in an error message The error message is identical to that of Item 1 b Next using the test data 05h an identical check is pe...

Page 251: ...e contro1 port 37 and the test data OOh is output to the data output port 378 Next input from the status port 379 the resu1t is OK if Bits 7 4 and 3 are 0 and Bits 6 and 5 are 1 If an error is detected the error message that identica1 to that of Item 1 is diap1ayed c Test data is output to the contro1 port and data output port so that each signal of the status port goes ON then the resu1ts are che...

Page 252: ... After attaching the loop back connector to the serial port issue the instruction to start this check SERIAL PORT CHECK Attach loop back connector to serial port Enter Y to start this check when connector is attached or Enter N to return to the menu The procedures for checking the serial port are as folIows 1 Input Output Check of MODEL Control Signal a Data Terminal Ready DTR 0 and Request to Sen...

Page 253: ...DSR ALWAYS LOW I I I I When CTS 0 I I I I Error code 1101 I ERROR RTS CTS CTS ALWAYS LOW I I I I 2 Data Transfer Check using Various Baud Rates The setting is fixed to even parity two stop bits and an eight bit data length The check data is 00 FFh A timeout check during data transmission and reception and a comparison check of the sent data and received data is performed The baud rates for perform...

Page 254: ...ta transmission or the Data Ready status is not assumed during data reception I I I I Error code 1102 TIME OUT ERROR I I I I Thesent data and received data is compared and theprogram displays an error message if they do not match xx yy 1103 Error code VERIFY ERROR Sent da ta Redeived data I I I I I I I I I I I I xx represents the sent data and yy representes the received data 3 Data Transfer Check...

Page 255: ...I I I I I I When the check is started the following message appreas Current test data is zz SERIAL PORT CHECK RS232C echo back check with various data format Current data format w data bits x stop bits parity yyyy I I I I I I I I I I I I I I w represents the data length of the current check x represents the stop bits yyyy represents the parity bit setting of NONE ODD EVEN SP ACED or MARKED and zz ...

Page 256: ... Enter Y to start this check when connector is attachd or Enter N to return to the menu Since the checking procedure for the alternate serial port is identical to that for the serial port its checking procedure is omitted here Only the differences are in port numbers and in the message titles I I I I Error code 1201 ERROR DTR DSR DSR ALWAYS HIGH or LOW ERROR RTS CTS CTS ALWAYS HIGH or LOW I I I I ...

Page 257: ...le times only the printer connection check is performed 1 Printer Connection Status Check A NULL code is output to the printer and the printer status is checked If an error is detected the corresponding error message is displayed DOT MATRIX PRINTER CHECK Error code 1401 Status Time out error Status 1 0 error Status Not on line Status Acknowledge error Status Busy Status Out of paper 2 Printing Che...

Page 258: ... detected during printing an error message is displayed that is identical to that of Item 1 REV A b Printing Check of Bit Images data The bit images data of OOH FFH are printed by the printer The data is printed after printing the following message I I I I Bit image data OOH FFH I I I I The control code for bit image printing is ESC K n1 n2 specification of single density bit images If an error is...

Page 259: ... following checks are consecutively execu ted in the order listed 1 Seek check 2 Write read check 3 Head select check 4 Error detection and correction check Each of the checking procedures are described as foliows 1 Seek Check The quantity of installed hard disk drives is first set using function 8 of int 13 The following message is displayed in case two hard disk drives are installed so input the...

Page 260: ...ed the error and y represents the head number 2 WRITE READ Check Drive selection is identical to that of Item 1 Next t a precaution is displayed when this check is started Enter Y to start this check Enter N to return to the menu I I The data on the highest physical cylinder may be destroyed l by this check I I I I I I The WRITE READ check performs a WRITE READ check for all sectors of all heads o...

Page 261: ...ase of read error I I I I I I I I I I I I I I I I xxx represents the number of the cylinder detected the error y represents the head number and zz represents the sector number 3 Head Selection Check Drive selection is identical to Item 1 The head selection check makes each head seek the maximum cylinder position then checks the head selection status I I I I HEAD SELECT CHECK I I I I If the head is...

Page 262: ...l read instrucion and the the following message is displayed if no error has been detected I I I I HARD DISK DRIVE S AND CONTROLLER CHECK Error code 1705 ERROR DETECTION ERROR I I I 1 b In the error correction check the test data 6db6h is prepared in the buffer then is written to the hard disk using the normal write instrucion Writing and reading are performed at Sector number 1 of the highest hea...

Page 263: ...urrent cylinder is xxx I I I I The xxx represents the number of the cylinder being read When the reading of all cylinders up to Cylinder No 0 is completed the results are displayed I I I I READ VERIFY CHECK I I I I BAD TRACKS xxxx READ ERROR TRACKS yyyy GOOD TRACKS zzz z I I I I Press ENTER to return to the menu I I I I xxxx represents the total number of bad tracks yyyy represents the total numbe...

Page 264: ...oop back connector to the alternate parallel port then issue the instruction to start the check I I I I I I I I I I Since the checking procedure for the alternate parallel port is identical to that for the parallel port its checking procedure is omitted here Only the differences are port numbers and the error message titles Data output port Status port Controll port 278h 279h 27ah I I I I ALTERNAT...

Page 265: ...A Board Unit ANT RM Board Unit ANT RMA Board Unit ANT MT Board Unit SPFG Board Unit Page 8 1 8 1 8 3 8 3 8 6 8 7 8 8 8 9 8 3 JUMPER SETTINGS 8 10 8 3 1 ANTA Board Jumper Settings 8 10 8 3 2 ANT RM RMA Board Jumper Settings 8 11 8 3 3 SPFG Board Jumper Settings 8 12 8 3 4 WHDC Board Jumper Settings 8 13 8 4 COMPATIBILITY LIST 8 14 8 4 1 Major Unit 8 14 8 4 2 P C 8 Unit 8 15 ...

Page 266: ......

Page 267: ...beeause the loeation of the option slot eonnee tor is ehanged Serial Modifieation Serial Number Plate B06 Alphabet A is prefixed No Number of the Serial Serial Number Plate 03 Y126041651 to the serial number Plate Number Plate Y126025251 Old 010001 New A010001 Code Label Modifieation No of the Code abbreviated abbreviated abbreviated Label SPFG Board Cireuit design SPFG board unit SPFG board unit ...

Page 268: ...to use a cation of the full len th Hard location of Disk Con roller the option slot connector ANT RMA ANT RMA board No ANT RMA board unit is ANT RMA board unit To keep constant parts No Board unit newly used Y12620900000 supply authorizea This is an alternative unit for the ANT RM board unit ANTA Board Circuit design ANTA board unit ANTA board unit 1 To increase CPU No modification Y12620500000 Y1...

Page 269: ...m 560hm X154413302 X154415602 Modification 10MHz 12MHz R39 R39 GAATCK 330hm GAATCK 560hm 50 50 SCLK CLK SCLK B3 C40 1 3C CN1 OC 2uH SCLK 34b 47PF l 6 3B GAATRF Description Unit CN5 B1 8042 2uH I I Countermeasure for FCC 1 I 1 TESTO C16 47pF I 3F 2 I J l VV o l j TE ST1 39 L J 1 B2 C42 2uH 1 120pF li lr C15 m m 47pF 1 Additional parts C41 X221221213 C42 2 Parts modification B1 X506000029 Y130202002...

Page 270: ... 2F Location 2E and 2F To improve DMAC clock cation of the Part NEC uPD8237AC 5 Part FUJITSU speed capability DMA controller X400082374 MB89237A P or X400892370 NEC uPD8237AC 2 6MHz version X400082371 5 Modifi Location 3E Location 3E Cost reduction cation of the Part INTEL Part INTEL timer counter 8254 2 8254 X400082541 X400082540 or INTEL 8254 2 X400082541 or AMD P82C54 X400825400 or AMD P82C54 2...

Page 271: ...20 Cost reduction 10 New Key I Location 3F board controlley Part C42051KA version Y126813000 o s J N C Q m D m Z m m Z To improve the execution speed of the keyboard controller Countermeasure for genius problem This circuit is not necessary because the computer system does not use 10MHz IRQ7 CN1 37a IR1 1 E Location 3F Part C42051KB Y126813001 GAATCX JOT JX201 4B open 11 X20a 12 i I 5 0 IR7 1 F 82...

Page 272: ...64 12 X400S04641 Location 21A and 22A Location 21A and 22A Part NEC Part NEC uPD4164C 12 uPD4164C 10 X40014164S X400141646 or MATSUSHITA MN4164P 12 X400041643 2 Modifi Location RL1 Location RL1 To adjust signal timing cation of the Part 200ns to e Part 1S0ns to e delay line chip XS1000 20 XS1000 90 3 Modifi Location 24A and 24B Location 24A and 24B 1 Cost reduction cation of the Part ATR B3 Y12681...

Page 273: ...Description Reason for Modification 10MHz 12MHz ANT RMA ANT RMA board Not installed Installed To keep constant parts Board unit newly Alternative unit for ANT RM supply authorizea board Xl I l tJ i JJ g Tl Tl m tJ m Z m CJ m m Z o I N Z o I I N ...

Page 274: ...d Countermeasure for FCC of the eable Part Cable set 5BT Y12620200000 set 5BT Y126303000 Y12620800000 2 Modifi 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 To allow a full length eation of the Hard Disk Controller to slot loeation CN CN be installed in eonneetor CN8 11 11 11 11 11 11 11 11 11 11 11 11 2 Tl Tl m tJ m Z o m m m m Z o 3 I N C I 3 I N tJ m ...

Page 275: ... 12MHz SPFG Board 1 Addition of GAATFD uPD765A 2 GAATFD J uPD765A 2 To solve the format a delay circuit B error with the 360KB or 1 I TI Y12720100001 I n 720KB FDD at 12MHz FDAN Y12720110000 IV Additional Parts R57 X154414720 R58 Xl I co c OJ g m c m Z C1 m OJ m Z o 3 J N o N 3 J N ...

Page 276: ...te 3 note 4 J6 A B B 1 wait cycle note 3 note 4 Slide switch settings Slide Switch 10MHz 12MHz Monitor select switch factory setting MONO factory setting MONO 11 11 I 11 11 I MONO COLOR MONO COLOR CPU speed select switch factory setting 8MHz factory setting 8MHz I 11 11 I I 11 11 I 6MHz 8MHz 10MHz 6MHz 8MHz 12MHz note 1 These selectable wait cycles are available during 10MHz note 2 These selectabl...

Page 277: ...ted J2 A A B B 256KB Disable upper 384KB B A A Prohib1ted 31 A B A B Prohibited B B A Prohibited B B B OKB Disable upper 640KB A A 128KB ROM size 27128 J4 B J4 A A B Prohibited B A Prohibited J5 B J5 A B B 256KB ROM size 27256 A A Select ROM sockets 24A 24B J6 A A B Prohibited B A Prohibited 31 A B B Select ROM sockets 23A 23B Not applicable Same as 10MHz co I Il iJ J 2 Tl Tl m Il m Z m m m Z o s ...

Page 278: ...FDC register set A A A Primary parallel I F IR 7 J3 A B A B Secondary 7arallel I F RQ5 J4 A A B A Parallel I F on video adapter IRQ7 J10 A B B Disable parallel I F A A A Primary serial I F IR 4 J5 A B A B Secondary serial I F RQ3 J6 A A B Disable serial I F J9 A B B Disable serial I F A AT com atible FDD I F J7 A B EPSON C AX FDD I F A Standard settins J8 A B Test mode of VC Not applicable Same as...

Page 279: ...nit J3 J2 J1 10MHz 12MHz 10MHz 12MHz WHDC B Select primary address sets J1 A Board A Select secondary address sets B Non latched status J2 B A Latched status B WAH mode J3 B A WA2 mode Not applicable Same as 10MHz co I CI D g b 1 Q Tl Tl m D m Z m m m Z o I N Z o I I N ...

Page 280: ...OK OK FD1157C OK OK MD5501 61 OK OK Display Mono MRS MO Board OK See 1 OK See 1 Adapter Color MRS CR Board OK OK MGA Board OK OK EGA Board OK See 2 OK See 2 Descriptions 1 Unit code Y14420620000 should be used 2 Unit code Y12720400001 Code view problem may occur Unit code Y12720400002 Code view problem is solved on this verSlon c TI m D m Z m CJ m m Z o s I N C I s I N D OJ ...

Page 281: ...00 OK See b Y12620200001 OK See b Y12620800000 See b OK SPFG Board Y12720100000 OK NG Y12720100001 OK NG Y12720110000 See a OK WHDC Board Y12720300000 See c d See c d Y12720310000 See c See c Y12720300001 See d See d Y12720310001 OK OK Descriptions a Should be OK but an additional compatibility check is required b The location of the option slot connectors are different c XENIX problem may occur d...

Page 282: ......

Page 283: ...eet 1 2 Sheet 2 2 Sheet 1 2 Sheet 2 2 Y12620300000 Y12620700000 Y12620900000 Yl2620200000 Yl2620200001 Yl2620800000 Y126501000 Yl2650100001 Yl26509000 Yl2720100000 Yl2720100001 Yl2720110000 A 9 A IO A IO A l1 A ll A ll A 12 A 13 A 12 A 13 A 14 A 15 A 17 A 15 A 17 A 16 A 17 WHDC Board Unit Y12720300000 A 18 Y12720310000 A 18 Y12720300001 A 18 Y12720310001 A 18 A 21 MGA Board Unit kEYBOARD FD1155C 1...

Page 284: ......

Page 285: ...EREQj RSTN STBI 10JlF VSS LCC k L VSS80286 1 ENAS OAKON u T c 68 P n SMIO OAK2NIU A CAP I N g I CPU g l I li IMiS BI E 4 2 O A U 1 1 012 I t O 4 011 Numerical XA4 u 9 A217 g o Processor E xt 2 A2Z OB DIS t 0l J S r 63 DIS E 5015 f XA7ME I H 5 9 07 014 014 5014 r I XAB u A PCKN I 6 g 013 1 013 0 5013 t I XA9 u C I DIP gg 012 1 5012 8 t XAIO CSOIN 7 4 0 7 I R 7 2ISi loai i i t lJ J 80287 8 g o 1 4 g...

Page 286: ...J _ C h ß3 2 1CLK 00 00 500 A BI XOO U SPEK C17 WJi VCC i8 5 A I 5 iI24Iiiil l mig 2 50245 g l DIR XAIS DXO Vl u bijil st h R22 VRI 0 f1t C3 Al L A XAI6 7 xX 1516 VOO C28 30K lOK lr 10V CN3 ß 8259A 2 r C32 J2 C 394 CKuCOO N G 02 045H 001132 6 5220 01 SKBN VSS O I 1 1 j r SPEAIIER 6 t t t l 28 Pinvss 14 13 t E L_ t l t 4 gg g NC V5S 1 h Li4NJM386 tKBDINHr SP EN 1 5 RESfi 1 al B g r 5 R37 IW l GNO O...

Page 287: ...jtt t tt r 1 t t t St3P g IRI AA4520 BB4 5 4 XD4lU VO 48 ROlli IRO CAS2 A3 B3 g l I Bt F9tHt INTA CASI A2 B2 1 XOI1Ul RTRW 5 I Im C1 W t IIm2 J e on gIU U 4 C17 W1i VCC 8 5 XAIS VOO R22 VRI t C3 CN3 8259A 2M l C32 XAI6 7 AI6 Eflf 71 C C28 30K 1 C K Il 8 0 1 SKBN VSS 0 1 1 R 23 3 l C t 5 M lJt f8l r 1 SPEAKER j6 28 P In v 55 14 NC VSS a __ _ I KBO INH 5 SP EN 1 R37 470A 4NJIo4386 lJIroalGNO 7 TO Jl...

Page 288: ...2 XAI6 7 XAI6 S I cC28 30K 1 1 01 SKIIN VSS 0 1 t ii l I 6 S O Oi t r SPEAKERj6 I t t l 28 Pinvss 14 1 NC VSS R23312 K8D INH S SP EN 1 R37 470A L 4NJM386 I oa oGND 7 TO J1 Slave 5 9100 n ON IRbS Interrupt Controll r I I I A 117 IA17 E 51 17 SA 17 1 mll i I m otm 1 1 22 8 LA19 s __ 4 I 6 t l_U J lu t t i t NC tm C2 u vcc AOXRW O I r GND8 SMRN 44 MEMRN SMWN MEMWN XMRN 10RN XMWN 10WN XIOAN DLA S8HEN ...

Page 289: ... l f b XA9lU C I t XAIO CSDIN it 7 4 D 7i rIR 7 2ISI I I 1 _J CSD2N D IR6 t 2 ALS245 ilt XAI3 CSIIN 4 OS IRS IR lE9U 11 XD7 XA14 xi g I 11 A Ilillllll I IX071U a02 1 E IR2 I 1 7 17 X06lUl URN U DI IAI A6 B6 X05IU NC 13 DO D 4 AT 46 t t1It1jtt tL tt r l 1 t lE8t O HIR O CAS2 f Al Il XD2IU ATDSt 26 INTA CASI f A2 12 OIIU ATRW S l J Im c m lIml J t A 11 XDOIU SPEK C17 Wli VCC 21 S V 71 C28 mr f1 3v C...

Page 290: ... NC 28 P 1 2 5 719 IJiQ W1IAll T rOGND 1 132 K Keyboard con ft ec t oir H h S f N C 2i7 Pl1 P26 20K rr lfß T 25BIOI L KBDCLK 1 B I S KBOCLK NC 1 TO P25 NC OSF 1 5406 fr s 3D PS IK 5 Q C12 DATA f C161 TC1S TESTl 2 NC rI R J 1 p Cll A26 24 z C4 Z7P Sg 12h SA S T f i7P 2 5 40 n 22 NC A211l 146818 VS5 ilL 1 0 0047 51K lOK 16VIO J 70 VOD P20 Oll 24 Pin A2S Ql 2 4D 13 TO I C14USlO C38 G A 11 M CMOS Re a...

Page 291: ...I 31 147 R 3B AEIII XIHEII AT VCC 31 05 39 RBTII RF20N I Iv 146 I 40 4 COFF RFIDII p tm 12EI L m I J OUTI I t Tvn 143 GIID H0 1_ 31b r i A2DMA2 RMIS 4 _ 41b t XAI AI 8237AC 1IS S 1Rii S 4 7K R_IWO l t tIE7 116 BIII i l j II SS 6I I 11 2OI 1031111111111111132b S oa 40 Pln Ili Ii 3 4 b 2b 470Q I VIl4 OS ORQ3 43b lt 04 ORQ2 44b XD3 03 J llll L_ I 00 Ittjt J L C L J 48 OMA Controller I 7 S _ 2 S 50 S ...

Page 292: ...CI411 114 I XAO 7 I L 9 B ce I I C W t0 I llM AI VCC 11 a e 17 71T E 26 2 a vcc Iili r c I 1 1r e XI41 iii T All _ _ _ _ I 27 COFI II VCC XAI O OJ 3BI B _ Cll _ 7 r I X _ I40 1I 1lC JII ffttij ii 1A4 CI7 11I Jofo lr N 49 GAATCK Oi iit lnfJ tO I_ lIAl XA4IHrl il GAATRF r _1 _ J O l 1 I 4l 5 32 VCC 28 BCA 00 rfr _ 1A f 7 3AI OMAI 2 12 1A1 b e XA7 XAI F WSlIl 111I To fJm i 8 AOMB89237A 3 1A1 8b C17 L...

Page 293: ... nr l l I 1_ 411 ALE oll r II II C C EL V jjDDD1 2 _1 V lfEY 9j a 1Zi l _W uJ 11 YDD R 022 9 18 IlI HNIß loH L 0 1 RE9 b2 8 FUJITSU v Rmr 74108 MB674 Jion Cf l L G JJ 549 48 VI fIL XIIEJIIW 021 llIIWIIu G lfff 114 3 A 111 T I IICI AI8I ii lH II eiß A Ne J 4 1 I 17 y 171ß T 33 34 31 41 51 M 33G W I 14 141ß 2 1I 44 I I i 1 EOI091EA 11 1 IIIß 64FLAT 5 40 I I ITSUCHlYAI 8 22 eIß 2 16BI 3 KlI11 Jmr II ...

Page 294: ... er III llr 3311 W 14 X A I 6 X A I 5 r IS lSt R R R R RI 1NE 20K A A A 16 20K oe 8 M L M M ME AOOOOOO A 1 0 000 e J o 8 B 8 I HJ2 J3 R 4 IS A A A w F I IS A A R2 MA IICI R IN I IICI Ne l IICI J J J J J RA E ER A A 0 F 0 A 11281 48 R R ce E YOD 21 ISV A A A A M VOD 1 3 RFHNIIl lOH L R I 0 1 1 NlUI VS9 FUJITSU vss M8674 VS9 549 48 vss llIilWIiIIl G tul TR r tNCl A 8 SAIIIlUI A Ne 4 17 1 17tul T 33 ...

Page 295: ...GOOO IOCHCK S07 S06 S05 S04 S03 S02 SOl SOO 10CHROY AEN SAII SAlB SAI7 SAI6 SAlli SAI4 SA13 SAI2 SAII SAIO SAI SAB SA7 SA6 SA5 SA4 SA3 SA2 SAI SAO RESET ORV IROI SMEMW SMEMR IOW IOR OACK3 OR03 OACKI OROI REFRESH CLK IR07 IR06 IROli IR04 IR03 OACK2 T C BAlE OSC OR02 OWS PG CNI CN2 5V r N 1CN4 4 bl I 1CN5 CN6 2 1CN7 5V I 3 12V CNa J ICN9 4 C6 C4 3 F ti 33 lF 12V AI 2 o L 3 16V r 16V 4 o L 5 6 o L 7 ...

Page 296: ......

Page 297: ...rror Input R28 R27 OT lOK 5 IK Vret RT CT 5 3 2 I 7 8 A 13 R3 R36 100 R39 3K 2K 09 R40 151588 _ 13K 1 012 I l R42 151588 R37 C13 J 51588 R44 3 61 10 T R41 4 7K 4 7K 1 4 7K R34 lOK R35 lOK R33 3 3K 2SC 1213A rc 2SCI213A DI Z _ R45 Q8 1 4 c I 4 7K 151588 R 013 43 100 1 K 151588 R46 TL CI2 6 8K 0 1 EQUIY 111 EPSON PC AX ATRPS UNIT THIC 35 BOARD UNIT NO Y126501000 y12650100001 7 _I 24 0 1 K IK RI5 RI7...

Page 298: ...10 W CRI02 CI24 4 7 lF 35V 10 W 0106 RI2 0114 CII3 CIIS RI23 CII6 0113 8 RI07 27 5W CI03 3300PF Z02 11 74V 12 35V 0101 I 1 5 r _ 12V 0102 RI02 47K 2W RIOI 47K 2W I 470 100 I leW YeW 9 4 71lF C7 r 0 35V RI7 1 8K leW RI05 RI03 1 20 YeW RI8 RI9 470 leW RI09 RIIO 40 40 5W 5W 3 I I I I I L _ RI6 RIS RI4 01 4 CI05 R26 560 laW 0103 FLIOI NTCIOI FIOI C IOI 5A 250V IOOOPF CRIOI CIOI 5 1000 CxlOI 200V IIlF ...

Page 299: ...C IZYDC 12YDC IRQ ORQZ GND 831 7407 LSIZSA LSI 4 5 4 J 2 1 4 EIA CARRER DETECT EIA DATA SET READY 1 EIA CLEAR TO SEND EIA RIIG IlDICATOR Z EIA RX DATA 1 I 42 Lr DATA7 6 S 4 4 3 CN 3 2 1 e BOXT e TA1T m T1 R I SLCT 12 PE 11 RIf 21_ WRT PROT 8 mm 18 li11f 20_ Sffi 32 HSi 24 WRT EN 30 e REAO OATI CN 2 o Tl C C EQUITY 111 EPSON pe AX SPFG BOARD SHEET 1 2 UNIT NO Y12720100000 y12720100001 A 15 ...

Page 300: ...SI215 71518 LSII 18FI 13DI 11581 13811 cO 4 EIA DATA TERMtiAL READlY 7 EIA REQUEST TO SEND 3 EIA TXDATA SIG GND CN4 EIA CARRER DETECT 6 EIA DATA SET READY 8 EIA CLEAR TO SEND EIA RtiG INDICATOR 2 EIA RX DATA DATA7 6 15 4 4 3 CN3 2 I 0 l 0 ST 08 AU 00 XT TIITT I SLCT 12 PE 11 0 RR 115 VI 0 i o o il il c z n l l Ci Z o o z z o l o 0 l l 0 l o o il il c z n l l Ci Z o o z z o l o 0 7 8 1 GND 81 810 8...

Page 301: ...GROUND PLANE One Point Earth D2 RI4 3 48K 1 RI5 1 74K 1 r I r t _ _ _ _ _ _ _ _ 1 2 0 Q R 3 4 f f lio 58 R R 17 18 ALSI13A RD GND TPI WINDOW WINDOW RD 2 3 4 T 3 4l J 5 TL081 Spare 2SAIOl5Y 01 R4 RI 4 1 2SAIOl5Y 02 R8 RII 4 7K RI3 3 3K DLY21500kbps EQUITY 1II EPSON pe AX SPFG BOARD SHEET 2 2 UNIT NO Y12720100000 Y12720100001 Y12720110000 3F 4 00 3F 6 OL Y 11300kbps 3F VCOSEL _ 13 12 DLYOl250kbps VC...

Page 302: ... Plnremovedl ii 7 I F j2 1 R 05 rl 5C 11 17 H51 OE I BCS STEPlj217 f l 12 7 13 1 wr 18 tm 6 I INDEX 21 INDEX es 10 A_ 11 12K 1 4W 2016 loons VCC GND Fi5CS t NC LNCIi P NC töMri P NCu 7 4 1 4 3 6F ll WDCS u H1il u mj HAI 4 WAUP C 6 WAUPL L P 1 HS3 4 HS2 4 HSI 4 HSO 4 4 5 l _ 4 I S07 I 61 I 41 31 2 1 1 O HD7 6 5 4 3 2 1 iöi row ALE 1171 1 1 4 SAU 7 1 3 OS 4i9 t R 6 l II OD HRST 1 4 5 1 1 5 0 1 YCCI ...

Page 303: ...7 19 D7 6 188 18 6 5 91 17 5 4 93 6 4 3 QI 3 2 94 2 I 92 I o l8i 0 MAI2 t 2 9 11 31 10 34 9 36 8 8 7 0 6 LlItI S OI I 4 3pi 1 LI 2 47 I 46 o r q RD h27 WRF RS 1 30 es GD7 _ I 6 t I L 1 5 1f_ _ 4 11_ gq 3 H__Hlt__ 2 H_ 1__ 2 I I OF 1rl t 4I I o 48 D WEHö r 4 2 _ WEHI t r 4 n 3 r ft öJ T i WELI 46 fA 1 4 7 CASL f RAS J r6 6 _ R R R R AAAA 321 0 NC IOO S 117l1 7ll MCCIRG8HV V MM AC 8 S L L G A M Y V ...

Page 304: ...r LS125 PI4 P 11 t 2 _10 L3 12 11 _ 180 Seroll PIO 1 13 rD r rl I__ l_ _ _ I PCJ 25 P13 4 u n AKO 5V P35 EI4 PCJ 9 EI8 PCJ IO EI7 PCJ II E20 PCJ 12 020 PCJ 13 C08 PCJ 14 B08 PCJ 15 BI9 PCJ 16 F08 PCJ 21 FI6 PCJ 20 E07 PCJ 19 009 PCJ 18 019 EI9 CI8 CI9 C06 C07 B06 B07 BI7 BI8 F06 F07 FI3 FI5 E05 E06 EI3 008 AIS AI6 EI6 FI4 AOI BOO 012 013 CIO CII C02 C03 B02 B03 BIO A05 F02 F03 F09 FIO EOI E02 E09 ...

Page 305: ...1 I rO I L 1 I O lO I SWFI SWF3 6 0 2 O 12 2PI 12 4HI L_ J 1fT LSSO 1_5 4 SF S _ _ f iWOSHI HDEOI 3 J liDO I TKOO 40 PRn 41 RDTO 9 7 RDYO 39 DCGO F I I I 3 I I HDE4 J 12 IHI 12 HI CI9 PSV R I I rC w 5F I lOK 2Lu 5F C31 LSI L 4 l R60 DEN 62 m 1 I 1 11 2 0 0 II II 0 i W Q LAMO 43 SPFI 41 PH41 47 PH31 46 PH21 4 PHII 42 50 HLDI HLFO 49 D LSI4 9 lOK R91 RII RI 3K RI3 5 6K lOK RI lOK RIO 6K 3K R70 3K R7...

Page 306: ......

Page 307: ...HW t 1 c B t t 1t 12 0 1 C39 19 T O OI F 10 HW i t t 1 t O R1I7 3 9K VOO IC6 20 HV 1 44 _ 0 J C40 HAI3426 21 TO OI llF HV F4 _ _ o 23 12 iCPI R4 2KJ C33y IIiF j fJ 14 CPO L w 4 XTAL R49 6 10KJ r EXTAL U TAII G CL CD 5 9 II Jl53 12J R50 56KG C31 1000PF R39 IKJ 02 15SIBI C32 O I F R96 IOKJ 4 Jl d 16 U5 14 C 3 2 b l J _ 0 552 RI03 2K 1 R94 __ R 5 R93 8 __ J r Ir I R46 L _ 4HIKNJIr _ jIr TRII I 2Sft62...

Page 308: ... LS688 I I IKx4 P7 Q7 t SWI A2B U i 3ifP6 I Q6 4lf hI j rv y o 29 11 P5 C Q51 iH 2HJ 30 I P4 I Q4 9 31 P3 Q3 I x P2 Q2 T T PI QI 5 PO 9 9 fu B130 ___i I JCi P Q PL nT N t r IIC31 r T J 1J1 l I I I I I I 200g l 4 WxB LS04 r A L S 5 6 3 6 I LEOI A2 n oiiLfOB QB r I 2 3 07 Q7 IoII 7 00 J 4 06 I Q6Pf lfIIIIL 3 5 05 C Q5 lill L 4 _ 5 6 04 4 Q4 II IIII L l oIIIl 6 7 7 03 Q3P I B 02 Q2P c _ M 1IiB 9 01 Q...

Page 309: ...Exploded Diagram For EQUITY m EPSON PC AX 2 2 I 500 134 132 126 300 A 25 103 ...

Page 310: ...201 125 230 108 100 Exploded Diagram For EQUITY m EPSON PC AX 1 2 231 241 A 26 ...

Page 311: ...oad Wanchai Hong Kong Phone 5 8314 OO Telex 65542 EPSON HX SEIKO EPSON CORPORATION 80 Hirooka Shiojiri shi Nagano 399 07 Japan Phone 0263 52 2552 Telex 3342 214 EPSON DEUTSCHLAND GmbH Zulplcher Strasse 6 4000 Dusseldorf 11 F R Germany Phone 0211 56030 Telex 8584786 EPSON FRANCE S A Evolic C 201 86 156 avenue Louis Roche 92230 Genneviliers Phone 1 4792 0113 Telex 614966 EPSON STI S A Paris 152 0803...

Page 312: ...EPSON Printed in Ja BIl 88 10 1 5 ...

Search results

Summary of Contents for PC AX

Reviews:

Related manuals for PC AX

Brands by name

Popular brands

Epson PC AX, Technical Manual

Search results

Summary of Contents for PC AX

Reviews:

Related manuals for PC AX

Brands by name

Popular brands