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PRELIMINARY

CYBLE-013025-00
CYBLE-013030-00

EZ-BLE™ WICED Module

Cypress Semiconductor Corporation

198 Champion Court

San Jose

,

CA 95134-1709

408-943-2600

Document Number: 002-xxxxx Rev. ** 

 Revised April 10, 2017

General Description

The  CYBLE-0130XX-00  is  a  fully  integrated  Bluetooth

  Low

Energy (BLE) wireless module solution. The CYBLE-0130XX-00

includes  onboard  crystal  oscillator,  passive  components,  flash

memory, and the Cypress CYW20737 silicon device. Refer to the

CYW20737 datasheet for additional details on the capabilities of

the silicon device used in this module. 
The  CYBLE-0130XX-00  supports  a  number  of  peripheral

functions  (ADC  and  PWM),  as  well  as  UART  serial

communication. The CYBLE-0130XX-00 includes a royalty-free

BLE  stack  compatible  with  Bluetooth  4.1  in  a  14.5  ×  19.2  ×

2.25mm package.
The  CYBLE-013025-00  includes  128KB  of  onboard  flash

memory and is designed to allow for self-sufficient opperation.

The  CYBLE-013030-00  does  not  contain  onboard  flash,

providing  maximum  cost  optimization  and  allowing  for  hosted

control or application RAM upload, or interface to external flash

on the host board. 
The  CYBLE-0130XX-00  is  fully  certified  by  Bluetooth  SIG  is

targeted  at  applications  requiring  cost  optimized  BLE  wireless

connectivity.  The  CYBLE-0130XX-00  is  footprint  compatible

[1]

with the CYBLE-x120xx-00 module family. 

Module Description

n

Module size: 14.52 mm × 19.20 mm × 2.25 mm 

n

Bluetooth LE 4.1 single-mode module

p

QDID: TBD

p

Declaration ID: TBD

n

Certified to FCC, IC, MIC, and CE regulations

n

Castelated solder pad connections for ease-of-use

n

128-KB flash memory, 60-KB SRAM memory

n

Up to 14 GPIOs configurable as open drain high/low, 

pull-up/pull-down, HI-Z analog, HI-Z digital, or strong output

n

Industrial temperature range: –30 °C to +85 °C

n

Cortex-M3 32-bit processor 

n

Watchdog timer with dedicated internal low-speed oscillator

n

Supports A4WP wireless charging

n

Supports fRSA encryption/decryption and key exchange 

mechanisms (up to 4 kbit)

n

Supports NFC tag-based “tap-to-pair”

n

Supports IR learning with built-in IR modulator

Power Consumption

n

Maximum TX output power: +4.0 dbm

n

RX Receive Sensitivity: –94 dbm

n

Received signal strength indicator (RSSI) with 1-dB resolution

n

TX current consumption: 9.1 mA 

n

RX current consumption: 9.8 mA 

n

Cypress CYW20737 silicon low power mode support

p

Sleep: 12 uA typical

p

Deep Sleep: TBD 

Functional Capabilities

n

10-bit auxiliary ADC with nine analog channels

n

Serial Communications interface (compatible with Philips

®

 I2C 

slaves)

n

Four dedicated PWM blocks 

n

BLE protocol stack supporting generic access profile (GAP) 

Central, Peripheral, Observer, or Broadcaster roles

n

Programmable output power control

Benefits

CYBLE-0130XX-00 provides all necessary components required

to operate BLE communication standards. 

n

Proven hardware design ready to use

n

Cost optimized for applications without space constraints

n

Non-volatile memory for complex application development

n

Over-the-air update capable for in-field updates

n

Bluetooth SIG qualified with QDID and Declaration ID 

n

Fully certified module eliminates the time needed for design, 

development and certification processes

n

WICED™ SMART provides an easy-to-use integrated design 

environment (IDE) to configure, develop, and program a BLE 

application

Notes

1. CYBLE-0130XX-00 global connections (Power, Ground, XRES, etc) are pad compatible with the CYBLE-x120xx-00 family of modules. Available GPIO and functions 

may not be 100% compatible with your design. A review of the pad location and function within your design should be complete to determine if the CYBLE-0130XX-00 

is completely pad-compatible to the CYBLE-x120xx-00 modules.

Summary of Contents for EZ-BLE WICED CYBLE-0130 00 Series

Page 1: ...temperature range 30 C to 85 C n Cortex M3 32 bit processor n Watchdog timer with dedicated internal low speed oscillator n Supports A4WP wireless charging n Supports fRSA encryption decryption and k...

Page 2: ...nizer 20 Receiver Signal Strength Indicator 20 Local Oscillator 20 Calibration 20 Internal LDO Regulator 20 Peripheral Transport Unit 21 Broadcom Serial Communications Interface 21 Peripheral Block 21...

Page 3: ...l guarantee that all mechanical specifications and module certifications are maintained Designs should be held within the physical dimensions shown in the mechanical drawings in Figure 2 on page 4 All...

Page 4: ...View See from Top Notes 2 No metal should be located beneath or above the antenna area Only bare PCB material should be located beneath the antenna area For more information on recommended host PCB la...

Page 5: ...ith the trace antenna located at the far corner This placement minimizes the additional recommended keep out area stated in item 2 Please refer to AN96841 for module placement best practices 2 To maxi...

Page 6: ...ers unless otherwise noted Pad length of 1 27 mm 0 635 mm from center of the pad on either side shown in Figure 7 is the minimum recommended host pad length The host PCB layout pattern can be complete...

Page 7: ...392 13 6 0 39 11 23 15 35 442 13 7 0 39 12 50 15 35 492 13 8 0 39 13 77 15 35 542 13 9 0 39 15 04 15 35 592 13 10 0 39 16 31 15 35 642 13 11 0 39 17 58 15 35 692 13 12 2 04 18 82 80 31 740 94 13 3 31...

Page 8: ...I2_MOSI master slave 3 3 ADC input QOC XTALI32K 5 P12 26 SPI2_CS slave 3 3 ADC input QOC XTALO32K 6 P15 3 ADC input SWDIO IR_RX 7 P14 38 SPI2_MOSI master slave 3 3 ADC Input IR_TX 8 P13 28 3 3 ADC inp...

Page 9: ...ADC input QOC IR_TX 9 P24 PUART_RX SPI2_CLK master slave 3 10 NC Not Connect 11 NC Not Connect 12 P25 PUART_RX SPI2_MISO maste r slave 3 13 P4 PUART_RX SPI2_MOSI maste r slave 3 IR_TX Q_Y0 14 P2 PUART...

Page 10: ...a known power on state This action can also be driven by an external reset signal which can be used to externally control the device forcing it into a power on reset state The XRES signal is an activ...

Page 11: ...Document Number 002 xxxxx Rev Page 11 of 42 PRELIMINARY CYBLE 013025 00 CYBLE 013030 00 Figure 8 illustrates the CYBLE 0130XX 00 schematic Figure 8 CYBLE 0130XX 00 Schematic Diagram...

Page 12: ...List Antenna Design Table 7 details trace antenna used in the CYBLE 0130XX 00 module For more information see Table 7 Table 7 Trace Antenna Specifications Component Reference Designator Description Si...

Page 13: ...ecryption and data dewhitening n Transmit Functions data framing FEC generation HEC generation CRC generation link key generation data encryption and data whitening Frequency Hopping Generator The fre...

Page 14: ...Modulator The CYBLE 0130XX 00 includes hardware support for infrared TX The hardware can transmit both modulated and unmodulated waveforms For modulated waveforms hardware inserts the desired carrier...

Page 15: ...etect both modulated and unmodulated signals For modulated signals the CYBLE 0130XX 00 can detect carrier frequencies between 10 kHz 500 kHz and the duration that the signal is present or absent The C...

Page 16: ...o help drive the charging circuitry for energy transfer as well as provide feedback for charging control The application and algorithm that drive the reference designs are available on request n Power...

Page 17: ...DC consists of an analog ADC core that performs the actual analog to digital conversion and digital hardware that processes the output of the ADC core into valid ADC output samples Directed by the fir...

Page 18: ...patch RAM code The SoC has a total storage of 380 KB including RAM and ROM The internal boot ROM provides power on reset flexibility which enables the same device to be used in different HID applicati...

Page 19: ...ircuit that completely resets all circuits to a known power on state An external active low reset signal XRES can be used to put the CYBLE 0130XX 00 in the reset state The XRES pin has an internal pul...

Page 20: ...in out of band attenuation enables the CYBLE 0130XX 00 to be used in most applications without off chip filtering Digital Demodulator and Bit Synchronizer The digital demodulator and bit synchronizer...

Page 21: ...e required on both the SCL and SDA pins for proper operation USupport for changing the baud rate during normal HCI UART operation is included through a vendor specific command that allows the host to...

Page 22: ...11 P27 Dual bonded only one of two is available n P12 P26 Dual bonded only one of two is available n P13 P28 Dual bonded only one of two is available n P14 P38 Dual bonded only one of two is available...

Page 23: ...p P13 on P13 28 n PWM0 3 Each of the four PWM channels contains the following registers p 10 bit initial value register read write p 10 bit toggle register read write p 10 bit PWM counter value regis...

Page 24: ...or the BBC n Physical layer packet handling turns RF on and off dynamically within packet TX and RX n Bluetooth specified low power connection mode While in these low power connection modes the CYBLE...

Page 25: ...VDD Power Supply Input 2 3 3 6 V VDD_RIPPLE Maximum power supply ripple for VDD input voltage 100 mV Table 15 ADC Specifications Parameter Symbol Conditions Min Typ Max Unit Number of Input channels 9...

Page 26: ...Digital Levels1 1 This table is also applicable to VDDMEM domain Characteristics Symbol Min Typ Max Unit Input low voltage VIL 0 4 V Input high voltage VIH 0 75 VDDO V Input low voltage VDDO 1 62V VI...

Page 27: ...tween power terminals Vdd using 90 efficient DC DC converter at 3V Operational Mode Conditions Typ Max Unit Receive Receiver and baseband are both operating 100 ON 9 8 10 0 mA Transmit Transmitter and...

Page 28: ...B C I 3 MHz adjacent channel 0 1 BER 27 dB C I image channel 0 1 BER 9 0 dB C I 1 MHz adjacent to image channel 0 1 BER 15 dB Out of Band Blocking Performance CW 1 2 30 MHz to 2000 MHz 0 1 BER3 3 Meas...

Page 29: ...47 0 dBm LO Performance Initial carrier frequency tolerance 150 kHz Frequency Drift Frequency drift 50 kHz Drift rate 20 kHz 50 s Frequency Deviation Average deviation in payload sequence used is 0000...

Page 30: ...requirements when operating in SPI Mode 0 and 2 and SPI Mode 1 and 3 respectively Table 21 UART Timing Specifications Reference Characteristics Min Max Unit 1 Delay time UART_CTS_N low to UART_TXD val...

Page 31: ...gure 17 SPI Timing Mode 1 and 3 BSC Interface Timing Table 23 BSC Interface Timing Specifications Reference Characteristics Min Max Unit 1 Clock frequency 100 kHz 400 800 1000 2 START condition setup...

Page 32: ...e 280 ns 9 Output valid from clock 400 ns 10 Bus free time2 650 ns 1 As a transmitter 300 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generati...

Page 33: ...operating and storage conditions for the Cypress BLE module ESD and EMI Protection Exposed components require special attention to ESD and electromagnetic interference EMI A grounded conductive layer...

Page 34: ...on a circuit different from that to which the receiver is connected n Consult the dealer or an experienced radio TV technician for help LABELING REQUIREMENTS The Original Equipment Manufacturer OEM m...

Page 35: ...ions 1 this device may not cause interference and 2 this device must accept any interference including interference that may cause undesired operation of the device Le pr sent appareil est conforme au...

Page 36: ...013030 00 MIC Japan CYBLE 0130XX 00 is certified as a module with type certification number TBD End products that integrate CYBLE 013025 00 do not need additional MIC Japan certification for the end p...

Page 37: ...details the orientation of the CYBLE 0130XX 00 in the tape as well as the direction for unreeling Figure 20 Component Orientation in Tape and Unreeling Direction TBD Table 25 Solder Reflow Peak Temper...

Page 38: ...etails reel dimensions used for the CYBLE 0130XX 00 Figure 21 Reel Dimensions The CYBLE 0130XX 00 is designed to be used with pick and place equipment in an SMT manufacturing environment The center of...

Page 39: ...cate the nearest Cypress office visit our website Table 27 Ordering Information Part Number CPU Speed MHz Flash Size KB RAM Size KB UART BSC I2C PWM Package Packaging CYBLE 013025 00 24 128 60 Yes Yes...

Page 40: ...Industry Canada IDE integrated design environment KC Korea Certification MIC Ministry of Internal Affairs and Communications Japan PCB printed circuit board RX receive QDID qualification design ID SM...

Page 41: ...LE 013025 00 CYBLE 013030 00 Document History Page Document Title CYBLE 0130XX 00 EZ BLE WICED Module Document Number 002 XXXXX Revision ECN Orig of Change Submission Date Description of Change PRELIM...

Page 42: ...ded only for reference purposes It is the responsibility of the user of this document to properly design program and test the functionality and safety of any application made of this information and a...

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